From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
Nicolas Dufresne <nicolas.dufresne@collabora.com>,
Chun-Kuang Hu <chunkuang.hu@mediatek.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes
Date: Wed, 14 May 2025 11:26:26 +0200 [thread overview]
Message-ID: <439db3ea-4fb7-4944-b182-222663c09b3d@collabora.com> (raw)
In-Reply-To: <20250514092259.47035-3-angelogioacchino.delregno@collabora.com>
Il 14/05/25 11:22, AngeloGioacchino Del Regno ha scritto:
> Add all of the Multimedia Data Path 3 (MDP3) related nodes
> including its Mutex instances, one for each VPPSYS block, and
> all of its DMA controllers, Film Grain (FG), HDR, Adaptive Ambient
> Light (AAL), Frame Resizer (RSZ), Tone Curve Conversion (TCC),
> Two-Dimensional Sharpness (TDSHP), and others, enabling the entire
> MDP3 macro-block.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Rob, sorry again for missing your previous email about the warnings
generated by this commit.
I ran a dtbs_check on this and I didn't see any warning - can you please urgently
check and confirm that I didn't miss anything on this one so that I can pull it in
the MediaTek trees for a fixed up PR?
If anything else is wrong with this one, I'll have to just drop it and delay this
for the next cycle as it's really too late (my bad, though).
Many many thanks,
Angelo
> ---
> arch/arm64/boot/dts/mediatek/mt8188.dtsi | 299 +++++++++++++++++++++++
> 1 file changed, 299 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 29d35ca94597..55260357ac66 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -2224,6 +2224,118 @@ vppsys0: syscon@14000000 {
> #clock-cells = <1>;
> };
>
> + dma-controller@14001000 {
> + compatible = "mediatek,mt8188-mdp3-rdma";
> + reg = <0 0x14001000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
> + mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
> + <&gce0 14 CMDQ_THR_PRIO_1>,
> + <&gce0 16 CMDQ_THR_PRIO_1>,
> + <&gce0 21 CMDQ_THR_PRIO_1>,
> + <&gce0 22 CMDQ_THR_PRIO_1>;
> + iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
> + mediatek,scp = <&scp>;
> + };
> +
> + display@14002000 {
> + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
> + };
> +
> + display@14004000 {
> + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14004000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
> + };
> +
> + display@14005000 {
> + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
> + };
> +
> + display@14006000 {
> + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14006000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
> + };
> +
> + display@14007000 {
> + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14007000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
> + };
> +
> + display@14008000 {
> + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
> + };
> +
> + display@14009000 {
> + compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
> + iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
> + };
> +
> + display@1400a000 {
> + compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
> + reg = <0 0x1400a000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_PADDING>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + display@1400b000 {
> + compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
> + reg = <0 0x1400b000 0 0x1000>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + display@1400c000 {
> + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x1400c000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> + iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
> + };
> +
> + mutex@1400f000 {
> + compatible = "mediatek,mt8188-vpp-mutex";
> + reg = <0 0x1400f000 0 0x1000>;
> + interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys0 CLK_VPP0_MUTEX>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
> + };
> +
> vpp_smi_common: smi@14012000 {
> compatible = "mediatek,mt8188-smi-common-vpp";
> reg = <0 0x14012000 0 0x1000>;
> @@ -2255,6 +2367,184 @@ vpp_iommu: iommu@14018000 {
> mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
> };
>
> + dma-controller@14f09000 {
> + compatible = "mediatek,mt8188-mdp3-rdma";
> + reg = <0 0x14f09000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
> + iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
> + };
> +
> + dma-controller@14f0a000 {
> + compatible = "mediatek,mt8188-mdp3-rdma";
> + reg = <0 0x14f0a000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
> + iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
> + };
> +
> + display@14f0c000 {
> + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14f0c000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
> + };
> +
> + display@14f0d000 {
> + compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
> + reg = <0 0x14f0d000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
> + };
> +
> + display@14f0f000 {
> + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14f0f000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
> + };
> +
> + display@14f10000 {
> + compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
> + reg = <0 0x14f10000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
> + };
> +
> + display@14f12000 {
> + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14f12000 0 0x1000>;
> + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
> + };
> +
> + display@14f13000 {
> + compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
> + reg = <0 0x14f13000 0 0x1000>;
> + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
> + };
> +
> + display@14f15000 {
> + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14f15000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
> + };
> +
> + display@14f16000 {
> + compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14f16000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
> + };
> +
> + display@14f18000 {
> + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14f18000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
> + };
> +
> + display@14f19000 {
> + compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
> + reg = <0 0x14f19000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
> + };
> +
> + display@14f1a000 {
> + compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
> + reg = <0 0x14f1a000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
> + };
> +
> + display@14f1b000 {
> + compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
> + reg = <0 0x14f1b000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
> + };
> +
> + display@14f1d000 {
> + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14f1d000 0 0x1000>;
> + interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
> + };
> +
> + display@14f1e000 {
> + compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
> + reg = <0 0x14f1e000 0 0x1000>;
> + interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
> + };
> +
> + display@14f21000 {
> + compatible = "mediatek,mt8188-mdp3-padding",
> + "mediatek,mt8195-mdp3-padding";
> + reg = <0 0x14f21000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
> + };
> +
> + display@14f22000 {
> + compatible = "mediatek,mt8188-mdp3-padding",
> + "mediatek,mt8195-mdp3-padding";
> + reg = <0 0x14f22000 0 0x1000>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
> + };
> +
> + display@14f24000 {
> + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f24000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> + iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
> + };
> +
> + display@14f25000 {
> + compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f25000 0 0x1000>;
> + #dma-cells = <1>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> + iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
> + };
> +
> wpesys: clock-controller@14e00000 {
> compatible = "mediatek,mt8188-wpesys";
> reg = <0 0x14e00000 0 0x1000>;
> @@ -2284,6 +2574,15 @@ vppsys1: syscon@14f00000 {
> #clock-cells = <1>;
> };
>
> + mutex@14f01000 {
> + compatible = "mediatek,mt8188-vpp-mutex";
> + reg = <0 0x14f01000 0 0x1000>;
> + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
> + };
> +
> larb5: smi@14f02000 {
> compatible = "mediatek,mt8188-smi-larb";
> reg = <0 0x14f02000 0 0x1000>;
next prev parent reply other threads:[~2025-05-14 9:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 9:22 [PATCH v2 1/3] dt-bindings: display: mediatek: Add compatibles for MT8188 MDP3 AngeloGioacchino Del Regno
2025-05-14 9:22 ` [PATCH v2 2/3] dt-bindings: media: mediatek: mdp3: " AngeloGioacchino Del Regno
2025-05-14 9:22 ` [PATCH v2 3/3] arm64: dts: mediatek: mt8188: Add all Multimedia Data Path 3 nodes AngeloGioacchino Del Regno
2025-05-14 9:26 ` AngeloGioacchino Del Regno [this message]
2025-05-14 12:56 ` Rob Herring
2025-05-14 13:02 ` AngeloGioacchino Del Regno
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