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Wed, 04 Jun 2025 10:05:30 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 554A5TEm005531 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Jun 2025 10:05:29 GMT Received: from [10.239.31.134] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Jun 2025 03:05:24 -0700 Message-ID: <43a6e141-adab-42e9-9966-ec54cb91a6de@quicinc.com> Date: Wed, 4 Jun 2025 18:05:21 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset To: Dmitry Baryshkov , Ziyue Zhang CC: , , , , , , , , , , , , , , , , , , , , References: <20250529035416.4159963-1-quic_ziyuzhan@quicinc.com> <20250529035416.4159963-3-quic_ziyuzhan@quicinc.com> <34dnpaz3gl5jctcohh5kbf4arijotpdlxn2eze3oixrausyev3@4qso3qg5zn4t> Content-Language: en-US From: Qiang Yu In-Reply-To: <34dnpaz3gl5jctcohh5kbf4arijotpdlxn2eze3oixrausyev3@4qso3qg5zn4t> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kr1ygYF-xldh2_nW38WLv7Xgzahp8F7z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA0MDA3NiBTYWx0ZWRfXydctOvOa9SmP /qo4oM6jGlGtQACfZRJfoYKTaT+0JMovEgzeaLABBzhhxSoeNFrgazYh/bLrGlaPROVjgG6VElB jEcJGd7ennwLg94abgN2FMZP5TaYC3ZtN08IG1fWFyaOKWQh17I1yR1Gx0ad8BCMJfFRvwf5GjP AIu9eD+6PMgzpGaI6DvCPzZsm+7WvqmwKd39DDeTn5jeS8dODGTJtWcaV+bjIP6Q/MqGI1l1xUI xnCrjAfMsaba9rtNIAjl7BRbOsnGbWrb//JpxgKl1fj0Z+8zLX3wNtR2FpdffEvDVZOhEGbCbWG HYV5sXx+phgwwmYtipQIaa7mKWb2pX/SLTiMntx7YU2a62RAQt+goxFDevDnC88x+c2fe66VbXz lfEa5xAF/86c4Ckt4viy9KwCvZjwtLfdslPcbkC44R6zEJeKkNK+9+Ixzxbogc8ckbl9jQpL X-Authority-Analysis: v=2.4 cv=RdWQC0tv c=1 sm=1 tr=0 ts=68401a6a cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=JfrnYn6hAAAA:8 a=COk6AnOGAAAA:8 a=gDmLj3BAQhsnJV4uteAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1CNFftbPRP8L7MoqJWF3:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: kr1ygYF-xldh2_nW38WLv7Xgzahp8F7z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-04_02,2025-06-03_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 phishscore=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 suspectscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506040076 On 6/4/2025 5:15 PM, Dmitry Baryshkov wrote: > On Wed, Jun 04, 2025 at 03:58:33PM +0800, Ziyue Zhang wrote: >> On 6/3/2025 9:11 PM, Dmitry Baryshkov wrote: >>> On Thu, May 29, 2025 at 11:54:14AM +0800, Ziyue Zhang wrote: >>>> Each PCIe controller on sa8775p supports 'link_down'reset on hardware, >>>> document it. >>> I don't think it's possible to "support" reset in hardware. Either it >>> exists and is routed, or it is not. >> Hi Dmitry, >> >> I will change the commit msg to >> 'Each PCIe controller on sa8775p includes 'link_down'reset on hardware, >> document it.' >> "Supports" implies that the PCIe controller has an active role in enabling >> or managing the reset functionality—it suggests that the controller is designed >> to accommodate or facilitate this feature. >> "Includes" simply states that the reset functionality is present in the >> hardware—it exists, whether or not it's actively managed or configurable. >> So I think change it to includes will be better. >> >> BRs >> Ziyue >> >>>> Signed-off-by: Ziyue Zhang >>>> --- >>>> .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++---- >>>> 1 file changed, 9 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml >>>> index e3fa232da2ca..805258cbcf2f 100644 >>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml >>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml >>>> @@ -61,11 +61,14 @@ properties: >>>> - const: global >>>> resets: >>>> - maxItems: 1 >>>> + minItems: 1 >>>> + maxItems: 2 >>> Shouldn't we just update this to maxItems:2 / minItems:2 and drop >>> minItems:1 from the next clause? >> Hi Dmitry, >> >> link_down reset is optional. In many other platforms, like sm8550 >> and x1e80100, link_down reset is documented as a optional reset. >> PCIe will works fine without link_down reset. So I think setting it >> as optional is better. > You are describing a hardware. How can a reset be optional in the > _hardware_? It's either routed or not. I feel a bit confused. According to the theory above, everything seems to be non-optional when describing hardware, such as registers, clocks, resets, regulators, and interrupts—all of them either exist or do not. Seems like I misunderstand the concept of 'optional'? Is 'optional' only used for compatibility across different platforms? Additionally, we have documented the PCIe global interrupt as optional. I was taught that, in the PCIe driver, this interrupt is retrieved using the platform_get_irq_byname_optional API, so it can be documented as optional. However, this still seems to contradict the theory mentioned earlier. >> BRs >> Ziyue >> >>>> reset-names: >>>> + minItems: 1 >>>> items: >>>> - - const: pci >>>> + - const: pci # PCIe core reset >>>> + - const: link_down # PCIe link down reset >>>> required: >>>> - interconnects >>>> @@ -161,8 +164,10 @@ examples: >>>> power-domains = <&gcc PCIE_0_GDSC>; >>>> - resets = <&gcc GCC_PCIE_0_BCR>; >>>> - reset-names = "pci"; >>>> + resets = <&gcc GCC_PCIE_0_BCR>, >>>> + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; >>>> + reset-names = "pci", >>>> + "link_down"; >>>> perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; >>>> wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; >>>> -- >>>> 2.34.1 >>>> >>>> >>>> -- >>>> linux-phy mailing list >>>> linux-phy@lists.infradead.org >>>> https://lists.infradead.org/mailman/listinfo/linux-phy -- With best wishes Qiang Yu