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([2a01:e0a:982:cbb0:c5b9:9b90:b1c4:1a1d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e81edasm163840315e9.15.2024.07.17.02.53.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jul 2024 02:53:51 -0700 (PDT) Message-ID: <43d6523e-d6b7-4fda-92bb-a52fcad2fdba@linaro.org> Date: Wed, 17 Jul 2024 11:53:50 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v3 2/3] clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE_PARENT flag To: Dmitry Baryshkov , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240716-topic-sm8650-upstream-fix-dispcc-v3-0-5bfd56c899da@linaro.org> <20240716-topic-sm8650-upstream-fix-dispcc-v3-2-5bfd56c899da@linaro.org> <9ad10d92-d755-4fae-b206-6e8648be6d48@linaro.org> <278354ec-532b-48de-8ee1-5477ddb4a285@linaro.org> <94e48e19-781e-4de3-a4e6-da8e923a1294@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/07/2024 11:49, Dmitry Baryshkov wrote: > On Wed, 17 Jul 2024 at 12:47, Konrad Dybcio wrote: >> >> On 16.07.2024 6:46 PM, Dmitry Baryshkov wrote: >>> On Tue, Jul 16, 2024 at 03:46:24PM GMT, neil.armstrong@linaro.org wrote: >>>> On 16/07/2024 15:44, Dmitry Baryshkov wrote: >>>>> On Tue, 16 Jul 2024 at 15:32, Neil Armstrong wrote: >>>>>> >>>>>> On 16/07/2024 13:20, Dmitry Baryshkov wrote: >>>>>>> On Tue, Jul 16, 2024 at 11:05:22AM GMT, Neil Armstrong wrote: >>>>>>>> Add the missing CLK_SET_RATE_PARENT for the byte0_div_clk_src >>>>>>>> and byte1_div_clk_src, the clock rate should propagate to >>>>>>>> the corresponding _clk_src. >>>>>>>> >>>>>>>> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") >>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>> Signed-off-by: Neil Armstrong >>>>>>>> --- >>>>>>>> drivers/clk/qcom/dispcc-sm8650.c | 2 ++ >>>>>>>> 1 file changed, 2 insertions(+) >>>>>>> >>>>>>> This doesn't seem correct, the byte1_div_clk_src is a divisor, so the >>>>>>> rate should not be propagated. Other platforms don't set this flag. >>>>>>> >>>>>> >>>>>> Why not ? the disp_cc_mdss_byte1_clk_src has CLK_SET_RATE_PARENT and a div_table, >>>>>> and we only pass DISP_CC_MDSS_BYTE1_CLK to the dsi controller. >>>>> >>>>> Yes, the driver sets byte_clk with the proper rate, then it sets >>>>> byte_intf_clk, which results in a proper divisor. >>>>> If we have CLK_SET_RATE_PARENT for byte1_div_clk_src, then setting >>>>> byte_intf_clk rate will also result in a rate change for the byte_clk >>>>> rate. >>>>> >>>>> Note, all other platforms don't set that flag for this reason (I think >>>>> I had to remove it during sm8450 development for this reason). >>>>> >>>> >>>> Ack, I think this deserves a comment explaining this, I'll add it. >>> >>> But where to place it? This applies to _all_ dispcc controllers. >> >> Commit message > > It is already committed. > The thing we keep adding new clock drivers based on previous ones that uses specific ops and flags with no documented reasons except in commit messages, but it's often buried into multiple cleanup changes. So at some point we should add simple comments before each special clock explaining what we're doing here, a good example is the clk_regmap_phy_mux_ops, where I had to dig into commit logs and understand why we handle it differently from downstream. Neil