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Mon, 09 Dec 2024 02:11:30 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B92BTKl028115 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 02:11:29 GMT Received: from [10.253.11.153] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 8 Dec 2024 18:11:26 -0800 Message-ID: <441f37f5-3c33-4c62-b3fe-728b43669e29@quicinc.com> Date: Mon, 9 Dec 2024 10:11:23 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node To: Andrew Lunn CC: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , , , , References: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> <20241118-dts_qcs615-v2-2-e62b924a3cbd@quicinc.com> <89a4f120-6cfd-416d-ab55-f0bdf069d9ce@quicinc.com> <3c69423e-ba80-487f-b585-1e4ffb4137b6@lunn.ch> <2556b02c-f884-40c2-a0d4-0c87da6e5332@quicinc.com> <75fb42cc-1cc5-4dd3-924c-e6fda4061f03@quicinc.com> <4a6a6697-a476-40f4-b700-09ef18e4ba22@lunn.ch> Content-Language: en-US From: Yijie Yang In-Reply-To: <4a6a6697-a476-40f4-b700-09ef18e4ba22@lunn.ch> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AyuOOpTBvZOEp_uonKIrjZUxjH_1zHuw X-Proofpoint-GUID: AyuOOpTBvZOEp_uonKIrjZUxjH_1zHuw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=705 priorityscore=1501 clxscore=1015 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090016 On 2024-11-29 23:29, Andrew Lunn wrote: >> I was mistaken earlier; it is actually the EMAC that will introduce a time >> skew by shifting the phase of the clock in 'rgmii' mode. > > This is fine, but not the normal way we do this. The Linux preference > is that the PHY adds the delays. There are a few exceptions, boards > which have PHYs which cannot add delays. In that case the MAC adds the > delays. But this is pretty unusual. After testing, it has been observed that modes other than 'rgmii' do not function properly due to the current configuration sequence in the driver code. > > If you decided you want to be unusual and have the MAC add the delays, > it should not be hard coded. You need to look at phy-mode. Only add Are you suggesting that 'rgmii' indicates the delay is introduced by the board rather than the EMAC? But according to the Documentation/devicetree/bindings/net/ethernet-controller.yaml, this mode explicitly states that 'RX and TX delays are added by the MAC when required'. That is indeed my preference. > delays for rgmii-id. And you then need to mask the value passed to the > PHY, pass PHY_INTERFACE_MODE_RGMII, not PHY_INTERFACE_MODE_RGMII_ID, > so the PHY does not add delays as well. > > Andrew -- Best Regards, Yijie