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Tue, 03 Mar 2026 10:08:26 -0800 (PST) X-Received: by 2002:a05:7301:fa10:b0:2b8:6896:d0e6 with SMTP id 5a478bee46e88-2be2342a21cmr1054995eec.7.1772561306037; Tue, 03 Mar 2026 10:08:26 -0800 (PST) Received: from [172.20.10.12] ([172.56.179.142]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be2afa297asm515339eec.23.2026.03.03.10.08.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 10:08:25 -0800 (PST) Message-ID: <4440a3a8-7281-4bea-bb84-7a9d19ef7ce9@oss.qualcomm.com> Date: Tue, 3 Mar 2026 10:08:23 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> <4pFL6wOeTKUt-Zq4YbjqJdacMgUIPSYJD-4-5DcIMEZ1sM7JsNFYcSv1bd7ZRVOklTsmkEfxM2b6tTflmiECNQ==@protonmail.internalid> <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDE0NSBTYWx0ZWRfX1UsarcqFrfC4 PgPy5Falj3VBxm+rmOF/LXyaGjyDxiFj6Za+LHnao/hMxO9Eld+j5mcFZdbXqfD6n2A5qE1XeJn g8CvLylKq8Z2m4E5gYUufEA8gZbWVg0xXSrlkSexhs1T7liw9J8sk5uvV3V1FCXdJWvy9sPt+oW LS6LN/uEcQTb5uPnxa+NL8o0kdDiZ+nVYGceF0qqn3b75TmUR4CcfW2Gut68g3PUzOqKCXyudxu 0/1rzkJQxy8wwNwDBH1OCXvlKTPR4ovKeSjlXv5Vin9Pv8rS/530093+7zQOh9eFhesbnqqTrad I54puVFSL7odkQuys9z3OGSLUut26lJo7cW1lyOWUHuchxyxcYYQKlbhHggdI/n8BbwsOvRGSLT 8Mq1UOvM44JYeb9vfYXsYcukA1HDcpQI/4l6zZNf74GlsRr9senLtv+3PG93wZ0LPfhPsFssgca C7SRX4gafdofeQRbVLA== X-Proofpoint-ORIG-GUID: LZmv1XoEHjdhhlmGI5qlopfGG5fC5fsL X-Authority-Analysis: v=2.4 cv=S+HUAYsP c=1 sm=1 tr=0 ts=69a7239b cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=393jXSRlBufqMOIp+yiRFw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=63XN3Wpy_Vpkm10PPgsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: LZmv1XoEHjdhhlmGI5qlopfGG5fC5fsL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-03_02,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030145 On 3/3/2026 1:27 AM, Bryan O'Donoghue wrote: > On 03/03/2026 01:51, Vijay Kumar Tumati wrote: >> Hi Bryan, >> >> On 2/26/2026 4:34 AM, Bryan O'Donoghue wrote: >>> Add a base schema initially compatible with x1e80100 to describe MIPI >>> CSI2 >>> PHY devices. >>> >>> The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices >>> have their own pinouts on the SoC as well as their own individual >>> voltage >>> rails. >>> >>> The need to model voltage rails on a per-PHY basis leads us to define >>> CSIPHY devices as individual nodes. >>> >>> Two nice outcomes in terms of schema and DT arise from this change. >>> >>> 1. The ability to define on a per-PHY basis voltage rails. >>> 2. The ability to require those voltage. >>> >>> We have had a complete bodge upstream for this where a single set of >>> voltage rail for all CSIPHYs has been buried inside of CAMSS. >>> >>> Much like the I2C bus which is dedicated to Camera sensors - the CCI >>> bus in >>> CAMSS parlance, the CSIPHY devices should be individually modelled. >>> >>> Signed-off-by: Bryan O'Donoghue >>> --- >>>    .../bindings/phy/qcom,x1e80100-csi2-phy.yaml       | 114 +++++++++ >>> ++++++++++++ >>>    1 file changed, 114 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100- >>> csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100- >>> csi2-phy.yaml >>> new file mode 100644 >>> index 0000000000000..c937d26ccbda9 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml >>> @@ -0,0 +1,114 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm CSI2 PHY >>> + >>> +maintainers: >>> +  - Bryan O'Donoghue >>> + >>> +description: >>> +  Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 >>> sensors >>> +  to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and >>> D-PHY >>> +  modes. >>> + >>> +properties: >>> +  compatible: >>> +    const: qcom,x1e80100-csi2-phy >>> + >>> +  reg: >>> +    maxItems: 1 >>> + >>> +  "#phy-cells": >>> +    const: 1 >>> + >>> +  clocks: >>> +    maxItems: 4 >>> + >>> +  clock-names: >>> +    items: >>> +      - const: csiphy >>> +      - const: csiphy_timer >>> +      - const: camnoc_axi >>> +      - const: cpas_ahb >>> + >>> +  interrupts: >>> +    maxItems: 1 >>> + >>> +  operating-points-v2: >>> +    maxItems: 1 >>> + >>> +  power-domains: >>> +    maxItems: 1 >>> + >>> +  vdda-0p8-supply: >>> +    description: Phandle to a 0.8V regulator supply to a PHY. >>> + >>> +  vdda-1p2-supply: >>> +    description: Phandle to 1.2V regulator supply to a PHY. >>> + >>> +required: >>> +  - compatible >>> +  - reg >>> +  - "#phy-cells" >>> +  - clocks >>> +  - clock-names >>> +  - interrupts >>> +  - operating-points-v2 >>> +  - power-domains >>> +  - vdda-0p8-supply >>> +  - vdda-1p2-supply >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> +  - | >>> +    #include >>> +    #include >>> +    #include >>> +    #include >>> + >>> +    csiphy@ace4000 { >>> +        compatible = "qcom,x1e80100-csi2-phy"; >>> +        reg = <0x0ace4000 0x2000>; >>> +        #phy-cells = <1>; >>> + >>> +        clocks = <&camcc CAM_CC_CSIPHY0_CLK>, >>> +                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, >>> +                 <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, >>> +                 <&camcc CAM_CC_CPAS_AHB_CLK>; >>> +        clock-names = "csiphy", >>> +                      "csiphy_timer", >>> +                      "camnoc_axi", >>> +                      "cpas_ahb"; >>> + >>> +        operating-points-v2 = <&csiphy_opp_table>; >>> + >>> +        interrupts = ; >>> + >>> +        power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> As we are cleaning up the PHY device nodes, we should consider fixing >> the power domains as well. Although TOP GDSC is defined as a power >> domain, it is not the power source for the PHY devices. Rather, it is >> the MMCX, MXC and optionally MXA based on the architecture (Refer to >> 'Voltage rail' column for PHY clocks in IPCAT). > > Feel free to send me a qcom laptop and I will :) :) > > From memory though I _thought_ only the TOP was required for the PHY. > I'd be grateful if you could confirm yourself in ipcat. > > - TITAN_TOP_GDSC > - MXC > - MMCX > - MXA - first time I've heard of this rail, from memory I don't remember >         having seen this in ipcat when I could do so. MCX and MMCX are comminly required power domains across the PHYs but a subset of PHYs have the dependency on MXA. > > There is no >> parent-child relationship between the TOP GDSC and these in the clock >> driver and it was just working as the required power rails are getting >> enabled by/for other MM devices. > > Well only the GDSC is supplied by the clock controller. Right, GDSC is controlled by the CAMCC to suspend the subsystems. But the actual power supply and the voltage rails are under the control of the RPMH. So the clients need to enable and vote for the required perf corner as the core clocks scale up/down to be independent of the other subsystems sharing those voltage rails. > >>> + >>> +        vdda-0p8-supply = <&vreg_l2c_0p8>; >>> +        vdda-1p2-supply = <&vreg_l1c_1p2>; >>> +    }; >>> + >>> +    csiphy_opp_table: opp-table-csiphy { >>> +        compatible = "operating-points-v2"; >>> + >>> +        opp-300000000 { >>> +            opp-hz = /bits/ 64 <300000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs_d1>; >>> +        }; >>> + >>> +        opp-400000000 { >>> +            opp-hz = /bits/ 64 <400000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>; >>> +        }; >>> + >>> +        opp-480000000 { >>> +            opp-hz = /bits/ 64 <480000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>; >>> +        }; >>> +    }; >>> >> Thanks, >> Vijay. > Thanks, Vijay.