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Thu, 17 Jul 2025 15:45:51 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 17 Jul 2025 15:45:50 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 17 Jul 2025 15:45:50 -0500 Received: from [128.247.81.81] (uda0499903.dhcp.ti.com [128.247.81.81]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56HKjooN2755246; Thu, 17 Jul 2025 15:45:50 -0500 Message-ID: <444774d0-5941-4428-b82e-d10b1fa099f2@ti.com> Date: Thu, 17 Jul 2025 15:45:50 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] Add Interrupts property for CDNS CSI2RX To: Yemike Abhilash Chandra , , CC: , , , , , , , , , References: <20250714092708.3944641-1-y-abhilashchandra@ti.com> Content-Language: en-US From: Jared McArthur In-Reply-To: <20250714092708.3944641-1-y-abhilashchandra@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 7/14/25 04:27, Yemike Abhilash Chandra wrote: > The driver patch that adds support for error detection on the > Cadence CSI2RX by enabling its interrupt lines was recently > picked up [0]. > > Accordingly, this patch adds the required interrupts property > to the Cadence CSI2RX device tree nodes. > > Test logs: > (To validate the complete functionality, CRC errors were > intentionally generated by modifying the sensor overlay) > > AM68: https://gist.github.com/Yemike-Abhilash-Chandra/123fed82e798a76944ec23f8e46d1114 > AM69: https://gist.github.com/Yemike-Abhilash-Chandra/1820e39888cb50e250a83e2d059365f6 > J721E: https://gist.github.com/Yemike-Abhilash-Chandra/63f993a995fd6a12cb113454952c063f > J722S: https://gist.github.com/Yemike-Abhilash-Chandra/2144fc8ab2f7bcdb3ef868e85424467d > J721S2: https://gist.github.com/Yemike-Abhilash-Chandra/f46587ec1ef72671ee31803dd93434b4 > J784S4: https://gist.github.com/Yemike-Abhilash-Chandra/0c594683772f11c70bccb508757e9799 > > Driver and Binding patch series: https://lore.kernel.org/all/20250416121938.346435-1-y-abhilashchandra@ti.com/ > > [0]: https://lore.kernel.org/all/aG9tuMFOnvwXkcE-@valkosipuli.retiisi.eu/ > > Yemike Abhilash Chandra (7): > arm64: dts: ti: k3-j721s2-main: Add interrupts property > arm64: dts: ti: k3-j721e-main: Add interrupts property > arm64: dts: ti: k3-j784s4-j742s2-main-common: Add interrupts property > arm64: dts: ti: k3-am62p-j722s-common-main: Add interrupts property > arm64: dts: ti: k3-j722s-main: Add interrupts property > arm64: dts: ti: k3-am62-main: Add interrupts property > arm64: dts: ti: k3-am62a-main: Add interrupts property > > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 +++ > arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 3 +++ > arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 +++ > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++ > arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 9 +++++++++ > arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 +++++++++ > 7 files changed, 39 insertions(+) > For the whole series. Reviewed-by: Jared McArthur -- Best, Jared McArthur