From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C56D4CD4937 for ; Thu, 21 Sep 2023 00:01:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229655AbjIUABw (ORCPT ); Wed, 20 Sep 2023 20:01:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229473AbjIUABv (ORCPT ); Wed, 20 Sep 2023 20:01:51 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F64183; Wed, 20 Sep 2023 17:01:44 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38KNgmq4004731; Thu, 21 Sep 2023 00:01:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=eZiEsQr4jDXdniIHO2huSgyccKHpg8Yu3cvM7FD3VGU=; b=i4arI0+jnZOFt18b36HQr4g4vWJOoBWUE6SUIZsE5SehP1gn3BwBQM5CBGPtec6gDeyB H/wAcF2GcIWEalFScwk2IRNZKmjKcclsmyigY/59Y243BQa+6O32hhjUTgZQxaH3pFfq I+WxxOPvqjm136M+X9BolzyQ4wCzb97vu1fa/bZfR1bR6ZFL44+4mYPS6SFB+LCEthwO N6uQ1hEo6Idbonxh5OxQiTiqMhGJyQmbGD/EiGX1Oe1V7ck/dCwrxa2rhPdiNzLbOqWP C17IAz/h1PdQOq7n/xcGehdyn2YLTv+c32MHZEV047KWLMk1kjmMB12fwoKoxTGuITbj Fg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t82mqh4xu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 00:01:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38L01aEh025595 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 00:01:36 GMT Received: from [10.71.111.102] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 20 Sep 2023 17:01:36 -0700 Message-ID: <444d125c-2a87-3bae-6ea0-b76dffeb63ef@quicinc.com> Date: Wed, 20 Sep 2023 17:01:35 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 2/3] drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280 Content-Language: en-US To: Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Kuogee Hsieh CC: , , , References: <20230921-topic-7280_dpu-v1-0-6912a97183d5@linaro.org> <20230921-topic-7280_dpu-v1-2-6912a97183d5@linaro.org> From: Abhinav Kumar In-Reply-To: <20230921-topic-7280_dpu-v1-2-6912a97183d5@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: b6-T_dA_x6yI4URcqmXp53mPJa227ExN X-Proofpoint-ORIG-GUID: b6-T_dA_x6yI4URcqmXp53mPJa227ExN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_12,2023-09-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200201 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/20/2023 3:46 PM, Konrad Dybcio wrote: > DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL > CFG 1.0.0. SC7280 is one of them. Add it. > sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and not dpu_hw_dsc_init. dpu_hw_dsc_init_1_2 assigns the dsc_bind_pingpong_blk op by default. So this change is not needed. > Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > index dc3198335164..b6a59d7b94c4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > @@ -164,7 +164,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = { > { > .name = "dce_0_0", .id = DSC_0, > .base = 0x80000, .len = 0x4, > - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), > + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL), > .sblk = &dsc_sblk_0, > }, > }; >