From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E628C433F5 for ; Thu, 31 Mar 2022 14:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237327AbiCaOL1 (ORCPT ); Thu, 31 Mar 2022 10:11:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232580AbiCaOLZ (ORCPT ); Thu, 31 Mar 2022 10:11:25 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23689184B6D; Thu, 31 Mar 2022 07:09:38 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id l9-20020a05600c4f0900b0038ccd1b8642so2083499wmq.0; Thu, 31 Mar 2022 07:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=message-id:date:mime-version:user-agent:content-language:to:cc :references:from:subject:in-reply-to:content-transfer-encoding; bh=u5RKTCIhVT0UdLD5a9lBWqntnPr7pNgupr5inV4aYmo=; b=Ro4qjQTYngAIqa+KiR2jjeeqVbD7TQOphkTqAOd+zRTPfvi/q+DLy38lEFB9e/nctR r9C2zey8bGqfLiHcRW7nudtjsB3uqDnkfVwY4GCxL0hyhF2DUSO2dZ7J8Y9hVZ8ireHf vcm6KXCJPWnBVOzzcw0LaLO0gA4h9C4yzHZiGjjNnQyoTn0z3xpsQ4BpJ168c5kkz052 LeHIMkk2tbZb0TretJ7hOKmyvl7hFwzGQs86zp5FhMo6h7HPnIRSgA+EEE0DJ8D3PxCE NhzyXk7ZeMi8LIDj84km1R83duFUydosQIamaHC/PBSv9tuCG2qOs+qHC1G4+ap+UG0R FoMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:to:cc:references:from:subject:in-reply-to :content-transfer-encoding; bh=u5RKTCIhVT0UdLD5a9lBWqntnPr7pNgupr5inV4aYmo=; b=6MAdxAk3yv3JBOxfxyO3aG3fr6vp08x8sQ/OQUWEj3aNv4bAEZNnvLpuKkY0kRgQS2 Z1a9wRIGB6dDI2aH7uBzAHugE8pwPXl3aPkX4WdofoZer9ffIGf+3bjeyE62BQ/suLNo MpO9h26HDFikeTMCA1euDGVHAUa3vT4pOvB/P+PVo+CECMkiVLgORLxmPgq9UX/rcotg k7FL/hCV57jgQDnsKwBOyW9eIFe1P/9x+vepK5ph+XV1hq56BWUSinGhuqFDQK42exmV 3RT5pdF49d2CCZMdip9LKzuEBFNZhqAh5AXLJvKTGydnT28VQljZ3MUOjgWLhLETverz LO9A== X-Gm-Message-State: AOAM533695RhVe1oPmVbrVmH3gPFeVL5maCx6PlBwQEzy8xh98EpWOQr /qFxJiKzng2vRUgl126Z7SY= X-Google-Smtp-Source: ABdhPJzLW7IbufpTDK9sgCBrOuZXAxLCMbpjDk5nnxZ5Ix8pSN5DFz1+MRhK5/qsv/pHBDz4RHy+2A== X-Received: by 2002:a7b:c925:0:b0:38c:82d7:868d with SMTP id h5-20020a7bc925000000b0038c82d7868dmr4701164wml.100.1648735776562; Thu, 31 Mar 2022 07:09:36 -0700 (PDT) Received: from [192.168.1.145] ([207.188.167.132]) by smtp.gmail.com with ESMTPSA id v15-20020a056000144f00b002057eac999fsm20704386wrx.76.2022.03.31.07.09.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Mar 2022 07:09:35 -0700 (PDT) Message-ID: <4452dd35-d4f4-66be-807b-7277cfd9a57b@gmail.com> Date: Thu, 31 Mar 2022 16:09:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Allen-KH Cheng , Rob Herring , Krzysztof Kozlowski Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu References: <20220330133816.30806-1-allen-kh.cheng@mediatek.com> <20220330133816.30806-5-allen-kh.cheng@mediatek.com> From: Matthias Brugger Subject: Re: [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes In-Reply-To: <20220330133816.30806-5-allen-kh.cheng@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/03/2022 15:38, Allen-KH Cheng wrote: > Add vcodec lat and core nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno Please drop reviewed-by as of comments below. > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 3d61238fb102..0b2b52a8f5ed 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1115,6 +1115,66 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; > }; > > + vcodec_dec: vcodec-dec@16000000 { > + compatible = "mediatek,mt8192-vcodec-dec"; > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ > + mediatek,scp = <&scp>; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; Change that was not part of the changelog. Please mention any change you make to the patch in the change log. > + #address-cells = <2>; > + #size-cells = <2>; Binding description says address-cells and size-cells should be of value 1. > + ranges = <0 0 0 0x16000000 0 0x26000>; > + > + vcodec_lat: vcodec-lat@10000 { > + compatible = "mediatek,mtk-vcodec-lat"; > + reg = <0x0 0x10000 0 0x800>; /* VDEC_MISC */ I suppose we would need to fix the reg value here then. Also IMHO the comment can be deleted. > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > + }; > + > + vcodec_core: vcodec-core@25000 { > + compatible = "mediatek,mtk-vcodec-core"; > + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ same here. Regards, Matthias > + interrupts = ; > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > + <&vdecsys CLK_VDEC_VDEC>, > + <&vdecsys CLK_VDEC_LAT>, > + <&vdecsys CLK_VDEC_LARB1>, > + <&topckgen CLK_TOP_MAINPLL_D4>; > + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > + }; > + }; > + > larb5: larb@1600d000 { > compatible = "mediatek,mt8192-smi-larb"; > reg = <0 0x1600d000 0 0x1000>;