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Sun, 09 Nov 2025 22:38:38 -0800 (PST) Message-ID: <4479a34b-58b3-45aa-9d2e-5e2a64f61e9d@linaro.org> Date: Mon, 10 Nov 2025 08:38:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba To: Haibo Chen , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev References: <20251110-nor-v1-0-cde50c81db05@nxp.com> <20251110-nor-v1-2-cde50c81db05@nxp.com> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <20251110-nor-v1-2-cde50c81db05@nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/10/25 6:02 AM, Haibo Chen wrote: > mt35xu512aba do not support chip erase command, and it contains one > die, and only support die erase. does this need a fixes tag then? With that: Reviewed-by: Tudor Ambarus > > Unfortunately the die erase opcode does not have a 4-byte opcode, > here forced to enter in the 4 byte address mode in order to benefit > of the die erase. > > Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf > Signed-off-by: Haibo Chen > --- Also, would you please help us with SFDP dumps, as you did in the next patches? It helps ups keep a database and update flashes to get rid of the non SFDP data. Thanks! > drivers/mtd/spi-nor/micron-st.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c > index 92eb14ca76c57f29ece1edb3fe652c56d1c2888f..89cd146095584ddebdd258a186f6398b420e5800 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -159,6 +159,22 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor) > return spi_nor_set_4byte_addr_mode(nor, true); > } > > +static int micron_st_nor_one_die_late_init(struct spi_nor *nor) > +{ > + struct spi_nor_flash_parameter *params = nor->params; > + > + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; > + params->n_dice = 1; > + > + /* > + * Unfortunately the die erase opcode does not have a 4-byte opcode > + * correspondent for these flashes. The SFDP 4BAIT table fails to > + * consider the die erase too. We're forced to enter in the 4 byte > + * address mode in order to benefit of the die erase. > + */ > + return spi_nor_set_4byte_addr_mode(nor, true); > +} > + > static void mt35xu512aba_default_init(struct spi_nor *nor) > { > nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; > @@ -189,6 +205,7 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) > static const struct spi_nor_fixups mt35xu512aba_fixups = { > .default_init = mt35xu512aba_default_init, > .post_sfdp = mt35xu512aba_post_sfdp_fixup, > + .late_init = micron_st_nor_one_die_late_init, > }; > > static const struct flash_info micron_nor_parts[] = { >