From: "Saripalli, RK" <rsaripal@amd.com>
To: Randy Dunlap <rdunlap@infradead.org>,
linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
Jonathan Corbet <corbet@lwn.net>
Cc: bsd@redhat.com
Subject: Re: [v2 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.
Date: Thu, 22 Apr 2021 16:23:14 -0500 [thread overview]
Message-ID: <4511e1d1-9ca9-c434-9a3f-322e54ffbe73@amd.com> (raw)
In-Reply-To: <6e755a24-1309-e75a-175c-196951f1167c@infradead.org>
On 4/22/2021 3:46 PM, Randy Dunlap wrote:
> On 4/22/21 12:32 PM, Saripalli, RK wrote:
>>
>>
>> On 4/22/2021 12:49 PM, Randy Dunlap wrote:
>>> On 4/22/21 10:10 AM, Ramakrishna Saripalli wrote:
>>>> From: Ramakrishna Saripalli <rk.saripalli@amd.com>
>>>>
>>>> ====================
>>>> Signed-off-by: Ramakrishna Saripalli<rk.saripalli@amd.com>
>>>> ---
>>>> .../admin-guide/kernel-parameters.txt | 5 +++++
>>>> arch/x86/include/asm/cpufeatures.h | 1 +
>>>> arch/x86/include/asm/msr-index.h | 2 ++
>>>> arch/x86/kernel/cpu/amd.c | 19 +++++++++++++++++++
>>>> 4 files changed, 27 insertions(+)
>>>
>>> as from v1:
>>
>> Randy, could you clarify your comments please?. Is there something here I need to change/clarify/fix?
>>
>
> Only that I had made these same comments (below)
> in v1 of the patch.
Yes I see them. I missed them. I will include them in the next patch release (batch them with other changes)
>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flkml%2F4c688fc7-67df-3187-54b2-bf20e510fb39%40infradead.org%2F&data=04%7C01%7Crk.saripalli%40amd.com%7Cfd08fbf7545d4c27c4cd08d905cfde95%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637547212629713144%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=hlGLgbZobkqXf3aBdMhSFC6Lg8nBLg1ssjHJDoyzI9s%3D&reserved=0
>
>>>
>>>> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
>>>> index 04545725f187..58f6bd02385b 100644
>>>> --- a/Documentation/admin-guide/kernel-parameters.txt
>>>> +++ b/Documentation/admin-guide/kernel-parameters.txt
>>>> @@ -3940,6 +3940,11 @@
>>>> Format: {"off"}
>>>> Disable Hardware Transactional Memory
>>>>
>>>> + predict_store_fwd [X86] This option controls PSF mitigation
>>>
>>> predict_store_fwd= ...
>>>
>>
>> OK
>>
>>>> + off - Turns on PSF mitigation.
>>>> + on - Turns off PSF mitigation.
>>>> + default : on.
>>>
>>> default: on.
>>>
>>
>> OK
>>
>>>> +
>>>> preempt= [KNL]
>>>> Select preemption mode if you have CONFIG_PREEMPT_DYNAMIC
>>>> none - Limited to cond_resched() calls
>
thanks,
RK
next prev parent reply other threads:[~2021-04-22 21:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-22 17:10 [v2 0/1] Introduce support for PSF control Ramakrishna Saripalli
2021-04-22 17:10 ` [v2 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control Ramakrishna Saripalli
2021-04-22 17:49 ` Randy Dunlap
2021-04-22 19:32 ` Saripalli, RK
2021-04-22 20:46 ` Randy Dunlap
2021-04-22 21:23 ` Saripalli, RK [this message]
2021-04-26 16:28 ` Reiji Watanabe
2021-04-26 16:40 ` Saripalli, RK
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