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Fri, 13 Mar 2026 04:42:40 -0700 (PDT) Message-ID: <451f74528021a67b40a4d08fdd0e5c80f6a90025.camel@linaro.org> Subject: Re: [PATCH v7 04/10] dt-bindings: soc: google: gs101-pmu: allow power domains as children From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Rob Herring Cc: Krzysztof Kozlowski , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown , Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Date: Fri, 13 Mar 2026 11:43:24 +0000 In-Reply-To: References: <20260306-gs101-pd-v7-0-03f7c7965ba5@linaro.org> <20260306-gs101-pd-v7-4-03f7c7965ba5@linaro.org> <20260312151228.GA3136988-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8+build1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-03-13 at 10:48 +0000, Andr=C3=A9 Draszik wrote: > On Thu, 2026-03-12 at 10:12 -0500, Rob Herring wrote: > > On Fri, Mar 06, 2026 at 10:29:55AM +0000, Andr=C3=A9 Draszik wrote: > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0 system-controller@17460000 { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible =3D "goog= le,gs101-pmu"; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg =3D <0x17460000 = 0x10000>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #address-cells =3D <1>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #size-cells =3D <1>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ranges; > > > =C2=A0 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 google,pmu-intr-gen-= syscon =3D <&pmu_intr_gen>; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pd_g3d: power-domain@1e00= { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 c= ompatible =3D "google,gs101-pd"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 r= eg =3D <0x1e00 0x80>; > >=20 > > I'm assuming 0x1e00 is an offset from 0x17460000. That's not what range= s=20 > > says though. It says both addresses are in the same address space=20 > > (system-controller@17460000 parent's address space). You need: > >=20 > > ranges =3D <0x0 0x17460000 0x10000>; >=20 > Thanks Rob! On gs101, the PD driver can not do direct mmio. Instead it > needs to use the regmap that the parent has created and apply the > offset from the PD's reg property (using struct resource::start) > (patch 7). >=20 > When using ranges as per your suggestion that doesn't work anymore, > as resource->start isn't the offset anymore but the final physical > address, and using that in combination with the parent's regmap > doesn't give us the right address anymore. >=20 > Is there an alternative other than using completely arbitrary indices > like e.g. rockchip is doing? My driver could of course peek into the parent and get the parent's IORESOURCE_MEM and subtract that start address to get the offset back. Is that considered clean (enough)? ppdev =3D to_platform_device(dev->parent); pres =3D platform_get_resource(ppdev, IORESOURCE_MEM, 0); pd->regmap =3D syscon_node_to_regmap(dev->parent->of_node); pd->configuration_reg =3D res->start - pres->start; pd->status_reg =3D res->start - pres->start; Cheers, Andre'