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b=WXpakY39+QdPdEW1vkErrXmAAViawX07De0phl0aaphXxHPixIAiIjH5K8UhH6nR8jmmWcXJmMrZuwhbislf6pwk8abErmeulLeGDN0WAknKRrnkM5/5u4oybO0hNv7rK/YOAH8upj16Rd2KmqQlDg24YoGqsjHbRjVXgEBkBKI= Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL1PR12MB5320.namprd12.prod.outlook.com (2603:10b6:208:314::17) by MN0PR12MB6054.namprd12.prod.outlook.com (2603:10b6:208:3ce::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.20; Wed, 7 Oct 2026 16:33:24 +0000 Received: from BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1]) by BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1%5]) with mapi id 15.21.0496.015; Wed, 7 Oct 2026 16:33:24 +0000 Message-ID: <45209a1b-5e52-4c50-a755-04affe312360@amd.com> Date: Wed, 7 Oct 2026 11:33:21 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] x86/resctrl: Fix ABMC counter programming To: Reinette Chatre , tony.luck@intel.com, bp@alien8.de Cc: x86@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, corbet@lwn.net, skhan@linuxfoundation.org, rdunlap@infradead.org, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, kas@kernel.org, rick.p.edgecombe@intel.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org References: <95bbc2e322ac18e2566c4963b7e6d13ac8485e20.1790976400.git.babu.moger@amd.com> Content-Language: en-US From: Babu Moger In-Reply-To: Content-Type: text/plain; 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On 10/6/26 12:47, Reinette Chatre wrote: > Hi Babu, > > On 10/2/26 2:26 PM, Babu Moger wrote: >> AMD's Assignable Bandwidth Monitoring Counters (ABMC) are configured via >> MSR_IA32_L3_QOS_ABMC_CFG. The architecture [1] received an update that >> expands the counter ID field (l3_qos_abmc_cfg.split.cntr_id) from 5 to 12 > > This describes an architecture change as a code change (l3_qos_abmc_cfg)? > > The subject also claims a "fix" but above establishes this just as an update because > of architecture change without making clear what the problem needing fixing is. > using the tip guidance when writing changelog will ensure that problem description > is always clear. Ack.> >> bits. >> > >> Use the updated field width. The number of supported counters is enumerated > > The second sentence of above paragraph seems out of place as it seems to add > in a bit of additional context as part of the rest of the paragraph that describes > the fix. > >> separately. Mark this as a fix to the original ABMC support to avoid > > Tag can speak for itself, just focus on describing the problem being fixed. > > The problem and fix are fused together making it difficult to see what is being > fixed here. Placing problem in its own paragraph helps to make this clear. > >> misconfigurations caused by truncating counter IDs on hardware that >> supports a large number of counters. >> >> Also limit the number of supported counters to the maximum value that can >> be represented by the 12-bit cntr_id field if hardware reports more than >> 12 bits. > > This is the actual fix though but is added as an afterthought? > Yea. >> >> The AMD64 Architecture Programmer's Manual [1], available at [2], will be >> updated in a future revision to document the expanded cntr_id field. > > > Consider an example changelog like below that aims to follow the x86 changelog > guidelines: > > AMD's Assignable Bandwidth Monitoring Counters (ABMC) are configured via > MSR_IA32_L3_QOS_ABMC_CFG; MSR_IA32_L3_QOS_ABMC_CFG.cntr_id selects which counter > the configuration applies to. The number of counters a platform supports (the > number of possible values written to MSR_IA32_L3_QOS_ABMC_CFG.cntr_id) is > enumerated separately via CPUID. > > On a platform that enumerates more than 32 counters, writing a counter ID > through the current 5-bit encoding truncates the ID and misprograms ABMC. > > The AMD64 Architecture Programmer's Manual [1], available from [2], has been > updated to widen MSR_IA32_L3_QOS_ABMC_CFG.cntr_id from 5 bits to 12 bits (the > published revision 3.41 does not yet reflect this; a future revision will). The > CPUID enumeration reports the maximum counter ID in a 16-bit field and can > still report more counters than a 12-bit MSR_IA32_L3_QOS_ABMC_CFG.cntr_id > can address. > > Widen MSR_IA32_L3_QOS_ABMC_CFG.cntr_id to 12 bits to match the architecture. Cap > the enumerated counter count at BIT(12) so every counter ID resctrl uses can be > written to MSR_IA32_L3_QOS_ABMC_CFG.cntr_id without truncation. > > Looks good. >> >> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming, >> Publication #24593, Revision 3.41, Section 19.3.3.3 "Assignable >> Bandwidth Monitoring (ABMC)" >> >> Fixes: 84ecefb76674 ("x86/resctrl: Add data structures and definitions for ABMC assignment") >> Signed-off-by: Babu Moger >> Cc: stable@vger.kernel.org >> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2] >> --- > Patch looks good to me. Thank you. Babu