From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
"Emil Renner Berthing" <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v2 3/6] dt-bindings: soc: starfive: syscon: Add optional patternProperties
Date: Mon, 20 Mar 2023 11:54:25 +0800 [thread overview]
Message-ID: <45221a1c-dc01-2759-3e32-658636625529@starfivetech.com> (raw)
In-Reply-To: <1f352445-4677-e33b-be14-c76bd7ffa188@linaro.org>
On 2023/3/19 20:28, Krzysztof Kozlowski wrote:
> On 16/03/2023 04:05, Xingyu Wu wrote:
>> Add optional compatible and patternProperties.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 39 ++++++++++++++++---
>> 1 file changed, 33 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> index ae7f1d6916af..b61d8921ef42 100644
>> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -15,16 +15,31 @@ description: |
>>
>> properties:
>> compatible:
>> - items:
>> - - enum:
>> - - starfive,jh7110-aon-syscon
>> - - starfive,jh7110-stg-syscon
>> - - starfive,jh7110-sys-syscon
>> - - const: syscon
>> + oneOf:
>> + - items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - const: syscon
>> + - items:
>> + - enum:
>> + - starfive,jh7110-aon-syscon
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - const: syscon
>> + - const: simple-mfd
>>
>> reg:
>> maxItems: 1
>>
>> +patternProperties:
>> + # Optional children
>> + "pll-clock-controller":
>
> It's not a pattern.
Does it use 'properties' instead of 'patternProperties'?
>
> Anyway should be clock-controller
Will fix.
>
>> + type: object
>> + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> + description: Clock provider for PLL.
>> +
>
> You just added these bindings! So the initial submission was incomplete
> on purpose?
>
> No, add complete bindings.
Does you mean that it should drop the 'description', or add complete 'description',
or add 'compatible', 'clocks' and 'clock-cells' of complete clock-controller bindings?
>
>> required:
>> - compatible
>> - reg
>> @@ -38,4 +53,16 @@ examples:
>> reg = <0x10240000 0x1000>;
>> };
>>
>> + - |
>> + syscon@13030000 {
>
> No need for new example... Just put it in existing one.
>
Actually, the PLL clock-controller are just set in sys-syscon resgisters. The stg-syscon and
aon-syscon don't need it. So PLL clock-controller node only is added in sys-syscon node.
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-03-20 3:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-16 3:05 [PATCH v2 0/6] Add PLL clocks driver for StarFive JH7110 SoC Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-03-19 12:25 ` Krzysztof Kozlowski
2023-03-20 2:41 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 2/6] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 3/6] dt-bindings: soc: starfive: syscon: Add optional patternProperties Xingyu Wu
2023-03-19 12:28 ` Krzysztof Kozlowski
2023-03-20 3:54 ` Xingyu Wu [this message]
2023-03-20 6:37 ` Krzysztof Kozlowski
2023-03-20 7:29 ` Xingyu Wu
2023-03-20 7:40 ` Krzysztof Kozlowski
2023-03-20 8:26 ` Xingyu Wu
2023-03-20 8:36 ` Krzysztof Kozlowski
2023-03-20 9:16 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 4/6] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-03-19 12:25 ` Krzysztof Kozlowski
2023-03-16 3:05 ` [PATCH v2 5/6] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 6/6] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
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