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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDA0MSBTYWx0ZWRfX5qGN6cYLASii hlFpaImyoD5Exb8c13iNBVSIka0nUkD4CkmpuOsm2nJyEUd3Hxy0wux1n1XY/yjCUpJB4wZrqaF AvkZCReiMQkqe1uqOOcjzdwK5+8Yudc= X-Proofpoint-ORIG-GUID: 95BprlWbmFkqYSzgXFosipWPHHaQzYr6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDA0MSBTYWx0ZWRfXxL3lftAN5rnu wZHuXNnMFU2Y35vODJu3evPePGqtw6j/ZNLCWAMHvzxzCQBqfur1vzgUbGHDTkzTEdRjT+XFSMR pV/ERCynNQJtNV1FZlqvfkgakeEaMm36elueBjRndE2BBL5qApGvH8sUce23PsZ0XgGgwqKdbt+ nW3mHZJxmmF+d5C9fWKMDKb7pqzPHqFNy/8/phL20yaQb8zGymrmE20UqpNPc0M0whSyiWuca9e WInKCIponuUDHRumczCy8MblSkdYVCh8L9fiIfVLPuNQY4d1Vrv7GXUyHi3EexfgSFMcjyShwgC yZRVbvImwlHukXk3G6RWXZXePNB5vLzd1j0YgH65rsGd8yA1PNCGn28N+ZbwOoePDTP9FbUiI0h B3L+PdY06yxjFeArUOXbbUD2JC9SC0CZ2Sf3B0+pjrkFFWSq2Pe+spFRazSr4KY4vg9x3jqlTx9 t0Hn8oKuxXjlJhnBXeA== X-Authority-Analysis: v=2.4 cv=E8BYNqdl c=1 sm=1 tr=0 ts=6ad0a955 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Z62H7OANAOBda0uacUIA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: 95BprlWbmFkqYSzgXFosipWPHHaQzYr6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150041 On 10/8/26 10:10 AM, Shawn Guo wrote: > The video clock controller binding describes three clock inputs for > Nord: the board XO, the always-on board XO and the 32 kHz sleep clock. > The videocc node instead passes the board XO and NW_GCC_VIDEO_AHB_CLK, > which is not an input of the controller. > > Pass bi_tcxo_ao_div2 and the board sleep clock in place of the AHB > clock. No functional change, NW_GCC_VIDEO_AHB_CLK is kept always on by > the NW GCC driver. > > Assisted-by: LLM > Signed-off-by: Shawn Guo > --- again, with the commit message fixed: Reviewed-by: Konrad Dybcio Konrad