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Tue, 15 Sep 2026 09:38:41 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v5 07/15] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Date: Tue, 15 Sep 2026 09:38:19 -0700 Message-ID: <45d72c3be850a5dc29f7695b244ce0da97f97f9e.1789446520.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A7FF:EE_|BY5PR12MB4307:EE_ X-MS-Office365-Filtering-Correlation-Id: 56bafd4b-e4a4-4310-823a-08df1347e00a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|23010399003|82310400026|1800799024|36860700016|5023799004|11063799006|56012099006|10067099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jhFz8SXhMXnWWDS8Lluzwe4aGdjpbfHpVZSmmDZ1Xec16QeRuxaLhuCnLvVbZ8qsmMjs7yQ3AbuVJXhYILR7XDqjIUWSDritS7tWejKJixc1CgnG0LY8BnLlJfunzhNuwKSvpOLLpwniCnR7nP0kzFkTplMzN4KtwvNjsTEmAEk+D+CCE8SBhgmKV1qb+g1mW1BQvM5YWF53ZfzNuOFG+epcNhF5LGjay6hq5TEq0zvpbOI6HS6etbZ8wHLZG6cxBD6fzPnMf6s09/C1crNjcRMC1rg5Bxj6gApsEilmEw1+XeiaxM5Mtp1WZUp1mf2054LNx7cMl5wpkBe5/HO7oGIYnIhe0liSB7XAS5BwzODVRdfonoBHZKhwEocS8f3TLEl0jfU4ROuZVMeWHnqNhGpgLweGmmn5buxG1lLHljgaGKK7SuvWAVXmzM6EunSp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 16:39:13.0310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56bafd4b-e4a4-4310-823a-08df1347e00a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A7FF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4307 From: Malak Marrid To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() must issue a CMDQ_OP_PRI_RESP back to the SMMU. Both EVTQ stall events and PRIQ requests reach the IOPF layer with the same IOMMU_FAULT_PAGE_REQ, but these two fault models are mutually exclusive. A stalling master holds a transaction until CMDQ_OP_RESUME and has no reason to send a page request. A later patch rejects PRI for such a master, so the response command can be selected from stall_enabled or pri_enabled. Note that a CMD_PRI_RESP.Resp encodes 0b00 as ResponseFailure (a permanent non-paging error), 0b01 as InvalidRequest (page-in unsuccessful), and 0b10 as Success. So IOMMU_PAGE_RESP_FAILURE maps to PRI_RESP_DENY (0b00) while IOMMU_PAGE_RESP_INVALID maps to PRI_RESP_FAIL (0b01), following the codes rather than the similarity of the enum names. Extend arm_smmu_enable_iopf() to also proceed for a PRI-enabled master, so that attaching a fault-capable domain would set up IOPF for it. Note that a later change will set master->pri_enabled, once all PRI paths are ready. Note: streams[0].id remains the RID because arm_smmu_enable_iopf() rejects num_streams != 1. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Reviewed-by: Jonathan Cameron Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++++++++------ 2 files changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 21b00b9296b31..558ba40f2f456 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1017,6 +1017,7 @@ struct arm_smmu_master { /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; + bool pri_enabled : 1; bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 0087a59da80de..9ebf3123e19d7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1039,32 +1039,68 @@ static int arm_smmu_wait_for_queue_drained(struct arm_smmu_device *smmu, return -ETIMEDOUT; } -static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused, +static void arm_smmu_page_response(struct device *dev, struct iopf_fault *evt, struct iommu_page_response *resp) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); - u8 resume_resp; + struct arm_smmu_cmd cmd; + int sid; - if (WARN_ON(!master->stall_enabled)) + if (WARN_ON_ONCE(evt->fault.type != IOMMU_FAULT_PAGE_REQ)) return; - switch (resp->code) { - case IOMMU_PAGE_RESP_INVALID: - case IOMMU_PAGE_RESP_FAILURE: - resume_resp = CMDQ_RESUME_0_RESP_ABORT; - break; - case IOMMU_PAGE_RESP_SUCCESS: - resume_resp = CMDQ_RESUME_0_RESP_RETRY; - break; - default: - resume_resp = CMDQ_RESUME_0_RESP_TERM; - break; + /* IOPF is gated to num_streams == 1 in arm_smmu_enable_iopf() */ + sid = master->streams[0].id; + + if (master->stall_enabled) { + u8 resume_resp; + + switch (resp->code) { + case IOMMU_PAGE_RESP_INVALID: + case IOMMU_PAGE_RESP_FAILURE: + resume_resp = CMDQ_RESUME_0_RESP_ABORT; + break; + case IOMMU_PAGE_RESP_SUCCESS: + resume_resp = CMDQ_RESUME_0_RESP_RETRY; + break; + default: + resume_resp = CMDQ_RESUME_0_RESP_TERM; + break; + } + cmd = arm_smmu_make_cmd_resume(sid, resp->grpid, resume_resp); + } else if (master->pri_enabled) { + struct iommu_fault_page_request *prm = &evt->fault.prm; + enum pri_resp pri_resp; + bool ssv; + + /* PCIe allows only one PRG Response per group */ + if (!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) + return; + switch (resp->code) { + case IOMMU_PAGE_RESP_SUCCESS: + pri_resp = PRI_RESP_SUCC; + break; + case IOMMU_PAGE_RESP_FAILURE: + /* 0b00 ResponseFailure: a permanent non-paging error */ + pri_resp = PRI_RESP_DENY; + break; + case IOMMU_PAGE_RESP_INVALID: + /* 0b01 InvalidRequest: page-in unsuccessful */ + pri_resp = PRI_RESP_FAIL; + break; + default: + WARN_ON(true); + return; + } + ssv = !!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); + cmd = arm_smmu_make_cmd_pri_resp(sid, resp->pasid, ssv, + resp->grpid, pri_resp); + } else { + WARN_ON_ONCE(1); + return; } - arm_smmu_cmdq_issue_cmd(master->smmu, - arm_smmu_make_cmd_resume(master->streams[0].id, - resp->grpid, - resume_resp)); + arm_smmu_cmdq_issue_cmd(master->smmu, cmd); /* * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP. * RESUME consumption guarantees that the stalled transaction will be @@ -3220,7 +3256,7 @@ static int arm_smmu_enable_iopf(struct arm_smmu_master *master, * device-specific fault handlers and don't need IOPF, so this is not a * failure. */ - if (!master->stall_enabled) + if (!master->stall_enabled && !master->pri_enabled) return 0; /* We're not keeping track of SIDs in fault events */ -- 2.43.0