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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LY0PR12MB727857.namprd12.prod.outlook.com (2603:10b6:408:3ba::5) by CH8PR12MB425199.namprd12.prod.outlook.com (2603:10b6:610:32d::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.10; Thu, 5 Nov 2026 16:06:32 +0000 Received: from LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522]) by LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522%5]) with mapi id 15.21.0592.009; Thu, 5 Nov 2026 16:06:32 +0000 Message-ID: <45e3d778-d484-4359-8d7b-edd1de303a2a@nvidia.com> Date: Thu, 5 Nov 2026 08:06:28 -0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration To: Richard Cheng Cc: Alison Schofield , Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Li Ming , Alex Williamson , vsethi@nvidia.com, alwilliamson@nvidia.com, Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , linux-tegra@vger.kernel.org References: <20261029145703.2185231-1-smadhavan@nvidia.com> <20261029145703.2185231-12-smadhavan@nvidia.com> Content-Language: en-US From: Srirangan Madhavan In-Reply-To: Content-Type: text/plain; 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>> + cxl_hdm_cache_set_dvsec_ctrl(pdev, ctrl); >> + return ret; >> } > Hmmm this change the old behavior that when "ctrl & PCI_DVSEC_CXL_MEM_ENABLE == val", > just return 1, it does cxl_hdm_cache_set_dvsec_ctrl() now, I wonder the reason ? > > Update software snapshot for the new design ? Hi Richard, Yes, it updates the software snapshot for the new design. A reset restores the cached DVSEC control value, so the cache has to match the live register even when MEM_ENABLE already matched. I added a comment saying so in v17. I also made cxl_set_mem_enable() return -ENODEV on an all-ones read, so that value is neither written back nor cached. -- Regards, Srirangan