From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751444AbdILJ1S (ORCPT ); Tue, 12 Sep 2017 05:27:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44446 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751214AbdILJ1Q (ORCPT ); Tue, 12 Sep 2017 05:27:16 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E0E486074C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vviswana@codeaurora.org Subject: Re: [PATCH v1 0/5] mmc: sdhci-msm: Corrections to implementation of power irq To: adrian.hunter@intel.com, ulf.hansson@linaro.org, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, asutoshd@codeaurora.org, stummala@codeaurora.org, riteshh@codeaurora.org, subhashj@codeaurora.org References: <1504097509-58983-1-git-send-email-vviswana@codeaurora.org> From: Vijay Viswanath Message-ID: <45f67de0-ba85-74b8-0dea-5b8e8a337dbe@codeaurora.org> Date: Tue, 12 Sep 2017 14:57:09 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1504097509-58983-1-git-send-email-vviswana@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Adrian, Ulf, I have addressed the comments on previous patch series. Can you please tell how I should proceed from here? Thanks, Vijay On 8/30/2017 6:21 PM, Vijay Viswanath wrote: > Register writes which change voltage of IO lines or turn the IO bus on/off > require sdhc controller to be ready before progressing further. Once a > register write which affects IO lines is done, the driver should wait for > power irq from controller. Once the irq comes, the driver should acknowledge > the irq by writing to power control register. If the acknowledgement is not > given to controller, the controller may not complete the corresponding > register write action and this can mess up the controller if drivers proceeds > without power irq completing. > > Changes since RFC: > wait_for_completion_timeout replaced with wait_event_timeout when > waiting for power irq. > Removed the spinlock within power irq handler and API which waits > for power irq. > Added comments to sdhci msm register write functions, warning that they > can sleep. > Sdhci msm register write functions will do a memory barrier before > writing to the register if the particular register can trigger > power irq. > Instead of enabling SDHCI IO ACCESSORS config in arm64/defconfig, it > will be selected in mmc/host/Kconfig if the platform is MMC_SDHCI_MSM. > > > Sahitya Tummala (2): > mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset > mmc: sdhci-msm: Add support to wait for power irq > > Subhash Jadavani (1): > mmc: sdhci-msm: fix issue with power irq > > Vijay Viswanath (2): > mmc: sdhci-msm: Add ops to do sdhc register write > mmc: Kconfig: Enable CONFIG_MMC_SDHCI_IO_ACCESSORS > > drivers/mmc/host/Kconfig | 1 + > drivers/mmc/host/sdhci-msm.c | 253 ++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 249 insertions(+), 5 deletions(-) >