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[95.49.125.236]) by smtp.gmail.com with ESMTPSA id u22-20020ac258d6000000b0049e9122bd1bsm216515lfo.164.2022.11.30.03.18.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Nov 2022 03:18:02 -0800 (PST) Message-ID: <46202b25-e253-0a5a-0c90-9d699906d3d7@linaro.org> Date: Wed, 30 Nov 2022 12:18:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH 07/12] arm64: dts: qcom: sm6115: Add dispcc node Content-Language: en-US To: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20221129204616.47006-1-a39.skl@gmail.com> <20221129204616.47006-8-a39.skl@gmail.com> From: Konrad Dybcio In-Reply-To: <20221129204616.47006-8-a39.skl@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29.11.2022 21:46, Adam Skladowski wrote: > Add display clock controller to allow controlling display related clocks. > > Signed-off-by: Adam Skladowski > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sm6115.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index 6d14bbcda9d3..ea0e0b3c5d84 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -4,6 +4,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -717,6 +718,19 @@ usb_1_dwc3: usb@4e00000 { > }; > }; > > + dispcc: clock-controller@5f00000 { > + compatible = "qcom,sm6115-dispcc"; > + reg = <0x05f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&sleep_clk>, > + <&dsi0_phy 0>, > + <&dsi0_phy 1>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > apps_smmu: iommu@c600000 { > compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; > reg = <0x0c600000 0x80000>;