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Wed, 06 Aug 2025 03:21:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGTKqHYf0s4xNLUVrvUtUmMVpKYxo7AnBKsVVS0NjaKjwOresU2P1m4/qqw3+J47JBXSXVmOA== X-Received: by 2002:a05:6a00:21cc:b0:76b:f16b:b186 with SMTP id d2e1a72fcca58-76c2b00506bmr2574586b3a.17.1754475708781; Wed, 06 Aug 2025 03:21:48 -0700 (PDT) Received: from [10.217.216.26] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbd7d1sm15188844b3a.80.2025.08.06.03.21.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 03:21:48 -0700 (PDT) Message-ID: <462b4010-fd79-4682-b9d2-31ffdd53b75a@oss.qualcomm.com> Date: Wed, 6 Aug 2025 15:51:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur To: Konrad Dybcio , Abel Vesa Cc: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> <3fc425fd-39fa-4efc-bc98-da86a88bfb1a@oss.qualcomm.com> <9e3b4706-c61a-4d69-be84-a5b6fc90eb35@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <9e3b4706-c61a-4d69-be84-a5b6fc90eb35@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 1ee0rHmxtxwfBn-QDNpc8Ai8sv_67f1E X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOCBTYWx0ZWRfX5s3LOzywwpd3 RMeMQti0zVgSSPyKQJtMJdmc9Qvxnooko9DcNHv8ZAoTPRsEFfnWXQt0biu0oboH2FdJu0TgNGx uXKGl0VyQY6ehOHJDswO0sPIpNhkNPSHfXexHU8f3YdEMkk2idCg4DMhjFVbAACw0KbonQKiz8x LbZRhv+iPt/EEhalMOBda0kAlhrvgRE5SjIxm/t/yjczEka2l0LTKdVTHqMIR03vuMSE9FKPS4P r2raBbCfjfi7XGN6sXyyXJdrH6DeDJRZTy8PV+Dz/t5vYZqJQIfQepr6mAY4xuhUTaCV4y9xSCZ 5xthnQikkeXhftsTeI45cDyEkJdUTaxviY0Smt7T8xkkJHIkMIKxh0X5MOBJy4OnwxTNPkVDV+G 4Nh0cHCY X-Authority-Analysis: v=2.4 cv=JIo7s9Kb c=1 sm=1 tr=0 ts=68932cc2 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=6OsRm2FtRiLRZBPAYcoA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: 1ee0rHmxtxwfBn-QDNpc8Ai8sv_67f1E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-06_02,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060008 On 8/6/2025 3:34 PM, Konrad Dybcio wrote: > On 8/4/25 4:21 PM, Taniya Das wrote: >> >> >> On 8/4/2025 6:40 PM, Konrad Dybcio wrote: >>> On 8/4/25 11:00 AM, Taniya Das wrote: >>>> >>>> >>>> On 8/1/2025 5:24 PM, Konrad Dybcio wrote: >>>>> On 8/1/25 7:31 AM, Abel Vesa wrote: >>>>>> On 25-08-01 10:02:15, Taniya Das wrote: >>>>>>> >>>>>>> >>>>>>> On 7/30/2025 4:55 PM, Abel Vesa wrote: >>>>>>>> On 25-07-29 11:12:37, Taniya Das wrote: >>>>>>>>> Add a clock driver for the TCSR clock controller found on Glymur, which >>>>>>>>> provides refclks for PCIE, USB, and UFS. >>>>>>>>> >>>>>>>>> Signed-off-by: Taniya Das >>>>>>>>> --- >>>>>>>>> drivers/clk/qcom/Kconfig | 8 ++ >>>>>>>>> drivers/clk/qcom/Makefile | 1 + >>>>>>>>> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ >>>>>>>>> 3 files changed, 266 insertions(+) >>>>>>>>> >>>>>>>> >>>>>>>> [...] >>>>>>>> >>>>>>>>> + >>>>>>>>> +static struct clk_branch tcsr_edp_clkref_en = { >>>>>>>>> + .halt_reg = 0x1c, >>>>>>>>> + .halt_check = BRANCH_HALT_DELAY, >>>>>>>>> + .clkr = { >>>>>>>>> + .enable_reg = 0x1c, >>>>>>>>> + .enable_mask = BIT(0), >>>>>>>>> + .hw.init = &(const struct clk_init_data) { >>>>>>>>> + .name = "tcsr_edp_clkref_en", >>>>>>>>> + .ops = &clk_branch2_ops, >>>>>>>> >>>>>>>> As discussed off-list, these clocks need to have the bi_tcxo as parent. >>>>>>>> >>>>>>>> Otherwise, as far as the CCF is concerned these clocks will have rate 0, >>>>>>>> which is obviously not the case. >>>>>>>> >>>>>>>> Bringing this here since there is a disconnect between X Elite and >>>>>>>> Glymur w.r.t this now. >>>>>>> >>>>>>> >>>>>>> The ref clocks are not required to be have a parent of bi_tcxo as these >>>>>>> ideally can be left enabled(as a subsystem requirement) even if HLOS >>>>>>> (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from >>>>>>> HLOS/APSS will not allow APSS to collapse. >>>>>> >>>>>> Is there a scenario where the APSS is collapsed and still the ref clock >>>>>> needs to stay enabled ? Sorry, this doesn't make sense to me. >>>>> >>>>> MDSS is capable of displaying things from a buffer when the CPU is off, >>>>> AFAICU >>>>> >>>>> We can do CXO_AO instead to have it auto-collapse if it's just Linux >>>>> requesting it to stay on, I think. >>>>> >>>> >>>> Thanks Konrad for adding the display use case. >>>> Abel, we earlier also had some PCIe, USB use cases where we had to leave >>>> the ref clocks ON and APSS could collapse. >>> >>> XO votes will prevent CX collapse, not APSS collapse. CX also powers >>> USB and PCIe so that only makes sense. >>> >>> I think it's fair to just stick XO as the parent of every refclock >>> today and think about the what-ifs (such as the mdss case I mentioned >>> above) later - especially since we have no infra to take full advantage >>> of it today (non-APSS RSCs etc.) >>> >> >> When ref clock have been part of GCC, then also they didn't have any xo >> as the parent, similar design we kept when it was moved to TCSR as well. > > Perhaps we've been running on luck (i.e. XO votes being cast through > another device / clock as a second order effect) all this time.. I'd > happily move towards formal correctness. > I would like to stay with no XO linkage to TCSR. Any driver has specific XO requirement should vote for the rpmhcc XO or XO_AO. -- Thanks, Taniya Das