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a="2167724" X-IronPort-AV: E=Sophos;i="6.27,186,1787036400"; d="scan'208";a="2167724" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2026 10:34:37 -0700 X-CSE-ConnectionGUID: Sc2vAOAbSfqxhqW7VjbayQ== X-CSE-MsgGUID: JhFRMV2QTAaJUSM7khis0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,186,1787036400"; d="scan'208";a="5513300" Received: from sghuge-mobl2.amr.corp.intel.com (HELO [10.125.109.85]) ([10.125.109.85]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2026 10:34:36 -0700 Message-ID: <462e07c4-ca77-4111-a4b7-c45bf8a71e3e@intel.com> Date: Fri, 30 Oct 2026 10:34:34 -0700 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] cxl/pci: Guard decoder accesses after reset To: Richard Cheng , jic23@kernel.org, dave@stgolabs.net, alison.schofield@intel.com, vishal.l.verma@intel.com, iweiny@kernel.org Cc: ming.li@zohomail.com, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com, mochs@nvidia.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260929020405.9724-1-icheng@nvidia.com> <20260929020405.9724-5-icheng@nvidia.com> From: Dave Jiang Content-Language: en-US In-Reply-To: <20260929020405.9724-5-icheng@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/28/26 7:04 PM, Richard Cheng wrote: > cxl_reset_done() runs even when PCI state restoration is skipped. > Reading HDM decoder registers while the device is inaccessible can > trigger another error. > > Skip decoder checks if the PCI Command read fails, returns all ones, or > Memory Space Enable is clear. > > Signed-off-by: Richard Cheng Reviewed-by: Dave Jiang > --- > drivers/cxl/pci.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index c7c91e8dc51d..2294f7761e50 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -976,6 +976,12 @@ static void cxl_reset_done(struct pci_dev *pdev) > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > struct cxl_memdev *cxlmd = cxlds->cxlmd; > struct device *dev = &pdev->dev; > + u32 command; > + > + /* PCI state restoration may have been skipped after a failed reset. */ > + if (pci_read_config_dword(pdev, PCI_COMMAND, &command) || > + PCI_POSSIBLE_ERROR(command) || !(command & PCI_COMMAND_MEMORY)) > + return; > > /* > * FLR does not expect to touch the HDM decoders and related