From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from latitanza.investici.org (latitanza.investici.org [185.218.207.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD506435A87 for ; Tue, 11 Aug 2026 12:50:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.218.207.228 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786452619; cv=none; b=eehlUbggBj0n9jTKZNF4vowHkzYIhhR0KbS3f6xLvnfEqkh1DXRE9A4smGNNtD130wrrkpJG5zOsShW6yHmZbg+vocuCtMKmXZpW05UcB9leMJ6OUM1Gz1uCwy3d61GYBDegZAmwXcuoxlwm8Lmtl8axIxsHJaMbUg+6FN38KwA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786452619; c=relaxed/simple; bh=K6fBgHbRtp7CXPyqevnKIwihpZtSdDyyQNKNwOKaJAY=; h=Date:From:To:CC:Subject:In-Reply-To:References:Message-ID: MIME-Version:Content-Type; b=bRBQNw4Z+VRnJK9xL/oeZjZIL8WFUB1vXo0vTdQ8dBCVD/BG+D4i1A3sC6G6ZONCS49oH9Ff0vzqnFICc8PCVUwsDIjkEtUFTc8OwN4TM7zSlJKXZeHc6EEiSh2+y2Woflc/7RbeBk9STovliltVHW+GyxC4Fux1OHUuuPtQfjI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net; spf=pass smtp.mailfrom=grrlz.net; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b=uUW+LGl4; arc=none smtp.client-ip=185.218.207.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=grrlz.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grrlz.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=grrlz.net header.i=@grrlz.net header.b="uUW+LGl4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grrlz.net; s=stigmate; t=1786452614; bh=WtFazJ4eDGxBIgrdgTbaPfe+cY7I7ADhXSuwt5WpCYE=; h=Date:From:To:CC:Subject:In-Reply-To:References:From; b=uUW+LGl4DKK98b94JOiKvdRuX8FKmHHlnfE7vjYqdQvtlLFweHJfdoB+eo8UXODm1 L9xCNo4WtWVwKoCH3tv3v3ofr0MSpT+AsmCQhnl7uNuOUvyX7uHIciF4QaWaAgWTjF nI1h7MzEGScJWS71J3QLiZV8FUEKPNiHsqM73qWM= Received: from mx3.investici.org (unknown [127.0.0.1]) by latitanza.investici.org (Postfix) with ESMTP id 4hKBKy5SgWzGpHK; Tue, 11 Aug 2026 12:50:14 +0000 (UTC) Received: by mx3.investici.org (Postfix) id 4hKBKy364HzGpDr; Tue, 11 Aug 2026 12:50:14 +0000 (UTC) Date: Tue, 11 Aug 2026 13:50:14 +0100 From: Bradley Morgan To: Will Deacon CC: Catalin Marinas , Mark Rutland , Pasha Tatashin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com Subject: =?US-ASCII?Q?Re=3A_=5BPATCH=5D_arm64=3A_hibernate=3A_pass_H?= =?US-ASCII?Q?VC=5FSET=5FVECTORS_args_to_the_resume_hvc?= In-Reply-To: References: <20260809213615.11646-1-include@grrlz.net> Message-ID: <463DA5C2-C933-45EC-A200-21AAF6258418@grrlz.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit On 11 August 2026 11:18:27 BST, Will Deacon wrote: >[+Maz, Pasha and James] > >On Sun, Aug 09, 2026 at 09:36:15PM +0000, Bradley Morgan wrote: >> swsusp_arch_suspend_exit() reinstalls the restored kernel's hyp stub >> vectors with an hvc, but never passes the arguments. x0 is not set to >> HVC_SET_VECTORS and x1 is not set to the vector address, so the stub >> dispatch falls through and returns without writing vbar_el2. EL2 is >> left pointing at the trans_pgd copy of the vectors, a page that >> swsusp_free() releases right after resume. >> >> Set the arguments up the same way __hyp_set_vectors() does. >> >> Fixes: 788bfdd97434 ("arm64: trans_pgd: hibernate: Add >trans_pgd_copy_el2_vectors") >> Cc: stable@vger.kernel.org >> Signed-off-by: Bradley Morgan >> --- >> arch/arm64/kernel/hibernate-asm.S | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/kernel/hibernate-asm.S >b/arch/arm64/kernel/hibernate-asm.S >> index 0e1d9c3c6a93..2baefe7a82d3 100644 >> --- a/arch/arm64/kernel/hibernate-asm.S >> +++ b/arch/arm64/kernel/hibernate-asm.S >> @@ -89,6 +89,8 @@ alternative_insn "dc cvau, x4", "dc civac, x4", >ARM64_WORKAROUND_CLEAN_CACHE >> isb >> >> cbz x24, 3f /* Do we need to re-initialise EL2? */ >> + mov x1, x24 >> + mov x0, #HVC_SET_VECTORS >> hvc #0 >> 3: ret >> SYM_CODE_END(swsusp_arch_suspend_exit) > >I'm having a really hard time figuring out what's supposed to be going >on here! > >The original hibernation code added by James in 82869ac57b5d ("arm64: >kernel: Add support for hibernate/suspend-to-disk") unconditionally >set the vectors in the exception handler: > >+el1_sync: >+ msr vbar_el2, x24 >+ eret >+ENDPROC(el1_sync) > >However, it _also_ set the vectors from C code in swsusp_arch_resume(): > >+ if (el2_reset_needed()) { >+ phys_addr_t el2_vectors = phys_hibernate_exit; /* base */ >+ el2_vectors += hibernate_el2_vectors - >+ __hibernate_exit_text_start; /* offset */ >+ >+ __hyp_set_vectors(el2_vectors); >+ } > >Later, Pasha refactored the assembly so that it could be shared with >kexec in 788bfdd97434 ("arm64: trans_pgd: hibernate: Add >trans_pgd_copy_el2_vectors"), however this added arguments to the >exception handler without updating the hypercall on the hibernation path. > >So I think we need to figure out: > >0. Whether this code is actually broken atm (I have a feeling it might > happen to work) Yes, since 788bfdd97434. >1. Why the original hibernation code set the vectors twice. They do different jobs. The C call parks EL2 on the safe page copy before the restore overwrites the current table. The asm call installs the final __hyp_stub_vectors afterwards. >2. Assuming they only need to be set once, whether we can drop the hvc > from the swsusp_arch_suspend_exit assembly code entirely. No. After the restore vbar_el2 is only writable from EL2, and the temporary copy cannot stay. swsusp_free() frees it right after resume. >3. Whether we can then drop the HVC_SET_VECTORS handling from this set > of vectors. > No, this hvc uses it, and so does kexec. >Will > Thanks!