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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc766554bsm343137766b.46.2026.02.17.03.15.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Feb 2026 03:15:17 -0800 (PST) Message-ID: <465ab63f-3d0c-46f7-a08e-cdc5fc26b600@oss.qualcomm.com> Date: Tue, 17 Feb 2026 12:15:12 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller To: Dmitry Baryshkov , Viken Dadhaniya Cc: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com References: <20260108125200.2803112-1-viken.dadhaniya@oss.qualcomm.com> <20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com> <5cdfe5a5-3c78-45a2-886c-768b224ad776@oss.qualcomm.com> <316fa702-6cd8-4842-aecf-c176a5a53e2e@oss.qualcomm.com> <5486697e-d02e-4b12-9a60-99d0de343515@oss.qualcomm.com> <2ho25tzct6t7gsuyufyg7m4a2ikmblhukb4uddwc7p35wd6yne@heippz3lh4kj> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <2ho25tzct6t7gsuyufyg7m4a2ikmblhukb4uddwc7p35wd6yne@heippz3lh4kj> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5MyBTYWx0ZWRfXzCMt67E7AOSi qO7KAHuV30G5sLIQQH7s9JtrnbCVzyz5bH3DLin6f+hWu6e52luFh9ksNaRPTbxksSY+ZMrRF9h NyVZVnJqKPfMV2v+8npNjXqqvO6LIr3NFht7j9mbbzajWpaEHZi4RxRKzWCHH1/AtLbLSwSGQML ntoek7xuTT+AdQtOWap3Fh+VKQAEZ31Nb89nyG1zt9G1++Hw29FOzJuagIEP6jqTpctlIrU5UQa sbZJUnA16rwub3+/CTZ3SnRxVGzsZDLHIl9lY4rvRDS8YJRxjQAlEvx6ZTRH01bAK/19MBvRrVP Xj6TbLA7d6gEyPnj3A4o4R+3ztj06aJjns/5Iy6+3inh5n59E3X3eUvaLnT5/1muYTSLIBZ976G 3Dll/dfV4LgMSwmlPAqukfU8ET5U3Im2thMWpLagPmJWlTnb4803oBkJmNkMUra/qb00AQlz0HU gFrMsJKTIGXB54IOIUQ== X-Proofpoint-ORIG-GUID: B6m9bSKABe4j3gMASHQA9YJWLQb2REQG X-Proofpoint-GUID: B6m9bSKABe4j3gMASHQA9YJWLQb2REQG X-Authority-Analysis: v=2.4 cv=Rfydyltv c=1 sm=1 tr=0 ts=69944dc8 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=l_9iY-1xcGPmI7VCd-QA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 clxscore=1015 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170093 On 2/4/26 2:09 AM, Dmitry Baryshkov wrote: > On Tue, Feb 03, 2026 at 05:07:11PM +0530, Viken Dadhaniya wrote: >> >> >> On 1/19/2026 11:59 AM, Dmitry Baryshkov wrote: >>> On Mon, Jan 19, 2026 at 10:21:37AM +0530, Viken Dadhaniya wrote: >>>> >>>> >>>> On 1/9/2026 7:35 PM, Dmitry Baryshkov wrote: >>>>> On Fri, Jan 09, 2026 at 06:23:39PM +0530, Viken Dadhaniya wrote: >>>>>> >>>>>> >>>>>> On 1/8/2026 7:33 PM, Dmitry Baryshkov wrote: >>>>>>> On Thu, Jan 08, 2026 at 06:22:00PM +0530, Viken Dadhaniya wrote: >>>>>>>> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform. >>>>>>>> The controller is connected via SPI3 and uses a 40 MHz oscillator. >>>>>>>> A GPIO hog for GPIO0 is included to configure the CAN transceiver in >>>>>>>> Normal mode during boot. >>>>>>> >>>>>>> The main question is: what is so different between RB3 Gen2 and previous >>>>>>> RB boards which also incorporated this CAN controller? Are there any >>>>>>> board differences or is it that nobody tested the CAN beforehand? >>>>>>> >>>>>> >>>>>> The behavior is consistent across platforms, but I do not have details on >>>>>> how other platforms were tested. >>>>>> >>>>>> On the RB3Gen2 board, communication with the PCAN interface requires the >>>>>> CAN transceiver to be in normal mode. Since the GPIO-controller support >>>>>> was recently integrated into the driver, I configured the transceiver using a >>>>>> GPIO hog property. Without this configuration, the transceiver is not set >>>>>> to normal mode, and CAN communication does not work. >>>>> >>>>> How do we verify the mode on a running system? I have the boards, but I >>>>> don't have anything connected to them over the CAN bus. >>>>> >>>>> BTW: can you recommend any simple setup to actually test the CAN bus on >>>>> those devices? >>>>> >>>> >>>> I tested the CAN controller using the following commands: >>>> >>>> 1. Loopback Mode Testing (GPIO hog not required) >>>> >>>> ip link set can0 down >>>> ip link set can0 type can bitrate 500000 loopback on >>>> ip link set can0 up >>>> cansend can0 12345678#1122334455667788_B >>>> candump can0 >>>> >>>> 2. Testing with External CAN FD Adapter (PCAN-USB FD) >>> >>> Thanks! It's price doesn't make it esily available, but it answers the >>> most imporant question: by the USB CAN adapter. >>> >>> Did you add >>> >>>> A GPIO hog was required to configure the transceiver in normal mode. >>> >>> I'd phrase it differently: to pull the transceiver out of standby mode. >>> By using the GPIO pin you make it always stay in the normal mode. It is >>> fine, but it is not optimal. Instead a proper solution would be to use >>> the MCP251XFD_REG_IOCON_XSTBYEN bit. Could you please instead implement >>> support for setting that bit, based on the DT property. >> >> Thanks for the suggestion. >> >> I tested enabling IOCON.XSTBYEN, but on this hardware it doesn’t bring >> the transceiver out of standby by itself. With only XSTBYEN set, the bus >> remains inactive and no frames reach the CAN adapter. Clearing LAT0 >> (driving GPIO0 low) is required to put the transceiver into normal mode; >> data transfer works only after LAT0 is cleared. > > Why? It should be doing exactly what is required. Could you please check > the voltage on the pin with the XSTBYEN bit set? If I'm interpreting the datasheet correctly, XSTBYEN only muxes the pin into its function and does *not* actually impact the operating mode, which would match what Viken is observing Konrad