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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e910f3sm273314866b.31.2025.07.11.02.57.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Jul 2025 02:57:05 -0700 (PDT) Message-ID: <465f4136-418e-48b8-93f4-e384244cb913@oss.qualcomm.com> Date: Fri, 11 Jul 2025 11:57:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset To: Krzysztof Kozlowski , Ziyue Zhang Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250625090048.624399-1-quic_ziyuzhan@quicinc.com> <20250625090048.624399-3-quic_ziyuzhan@quicinc.com> <20250627-flashy-flounder-of-hurricane-d4c8d8@krzk-bin> <1606591b-5707-48bf-8f60-44063ecf8f1a@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <1606591b-5707-48bf-8f60-44063ecf8f1a@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Ar7u3P9P c=1 sm=1 tr=0 ts=6870dff4 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=00NdyYYEmPKBbhCvcP8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: CieoAbPsR5-Djq_-nv6xYSvHHOeoyyyh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzExMDA3MCBTYWx0ZWRfXxmApSB6y4uyY 30MvXnNCJFP2cWbWS0/6r7aJnca4ii+psaD4jnCfSVi7vyrnF0/scLqsqz/3PjpgDtadyThK3QB cDfe8t8roIAXKYAui8C3+hVxrliCpMZ9iS3umzP8A8yZL0ocOH0FCXPGr/xwpjbxy5aG2aGqFsl UnJ9hrnQzOmE8LAfY2Mzdbvgzbg3EKCjWD4nRbyIiErB2jfieCOpp215c3IMei+Rz1OtRiXCjT4 TNjDwxDxq7XTpNbPYrpyHgyj5YtghcmODD141G8mEZmd9y9iBGdHe/1PgG88MikRYqqzYvH1ABb Cgr3qijdm6m+UxZquXxzp7QJDcVqmljny4P06qdi32kHEb7rtUTUTJXMYcJPD7051TEsyqr3Vap XheACKz3suFFd6R2OrsnDc6Uf58J8I4IWwebTvphkZkUzwcbT2pIBAVWI31JzvrDvSoJJ03N X-Proofpoint-GUID: CieoAbPsR5-Djq_-nv6xYSvHHOeoyyyh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-11_03,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=514 clxscore=1015 adultscore=0 phishscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507110070 On 7/11/25 10:44 AM, Krzysztof Kozlowski wrote: > On 11/07/2025 10:26, Ziyue Zhang wrote: >> >> On 6/27/2025 3:08 PM, Krzysztof Kozlowski wrote: >>> On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote: >>>> Each PCIe controller on sa8775p includes 'link_down'reset on hardware, >>>> document it. >>> This is an ABI break, so you need to clearly express it and explain the >>> impact. Following previous Qualcomm feedback we cannot give review to >>> imperfect commits, because this would be precedent to accept such >>> imperfectness in the future. >>> >>> Therefore follow all standard rules about ABI. >>> >>> Best regards, >>> Krzysztof >> >> Hi Krzysztof >> >> >> This does not break the ABI. In the Qualcomm PCIe driver, we use the APIs >> devm_reset_control_array_get_exclusive, reset_control_assert, and > > I see in the binding requirement of 1 reset before and after your patch: > requirement of two reset lines. > > This is an ABI change. My entire comment stays valid, so don't just > deflect it but resolve it. Ziyue, the change is good, but it needs a better explanation. Try something like: SA8775P PCIe RCs include two reset lines: a core one ("pci") used to reset most of the block, and a "link_down" one, used to ABCDXYZ. As the latter was omitted with the initial submisison, describe it. Because ABCDXYZ is not required for most of the block's functionality, devicetrees lacking it will not see much of a difference - it is however required to ensure maximum robustness when shutting down the core. ---- Note that there are physically more reset lines going to/near the RC, but many of them are either inaccessible to the OS, or very much should never ever be. This is the case with most hw blocks, so don't be surprised if you see a list with more than these two. I believe "pci" and "link_down" are the only ones intended for OS consumption. You can see some of that bleeding out to Linux on e.g. some IPQ platforms that don't have a separate MCU (some flavor of RPM) that would do the bus management. Konrad