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(p200300ea8f1e38001889225f1b5b4b37.dip0.t-ipconnect.de. [2003:ea:8f1e:3800:1889:225f:1b5b:4b37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43970d54754sm644661f8f.36.2026.02.20.13.30.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Feb 2026 13:30:37 -0800 (PST) Message-ID: <4674c965-f4d1-4ba9-9e36-9d3bbbb37f64@gmail.com> Date: Fri, 20 Feb 2026 22:30:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v2] net: phy: micrel: Add support for lan9645x internal phy To: "Russell King (Oracle)" Cc: Jens Emil Schulz Ostergaard , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , o.rempel@pengutronix.de, Steen Hegelund , Daniel Machon , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260130-phy_micrel_add_support_for_lan9645x_internal_phy-v2-1-202ac31cf9c4@microchip.com> <92ba22ee64b2670448295b44d663d8ae7e8fe9c4.camel@microchip.com> <641d92a2-93fb-4ffe-89d8-77bf10edecf8@gmail.com> <1b14f42944d21fff1cb45132fe6dc9e5c18289a1.camel@microchip.com> <00f03a3f-fc12-4875-b4b5-7470e7f0452d@gmail.com> Content-Language: en-US From: Heiner Kallweit In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 20.02.2026 22:10, Russell King (Oracle) wrote: > On Fri, Feb 20, 2026 at 09:50:44PM +0100, Heiner Kallweit wrote: >> No, BMCR_RESET usually doesn't reset configuration registers. That's why the >> function is called genphy_*soft*_reset. In case your PHY behaves different, >> which configuration registers does it change? > > I don't think your statement is correct. > > Looking at AR8035 for example, the WoL interrupt enable is doumented as > being cleared on soft reset. Smart Speed configuration also gets reset. > > 802.3 22.2.4.1.1 states that setting 0.15 results in the status and > control registers shall be set to their default states. > > So, we should not assume that setting 0.15 will retain configuration in > the PHY - at least phylib should not assume that a call to > genphy_soft_reset will not clear the configuration registers. If we > have code in phylib that makes that assumption, phylib is buggy to > 802.3. > Indeed I was wondering why c22 states "reset control registers" whilst the PHY's I'm dealing with don't do this. At least for the Marvell PHY's I used the spec says "resets PHY state machine". For Realtek the spec statement was "resets BMCR and BMSR". And often config bits are described as "becomes effective after reset". But yes, there may be PHY's implementing exactly the c22 behavior, so we shouldn't rely on "soft" in general.