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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 8unbbFT5SddJXJJPJZJ4TNG9UItmnBVz X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDIwMCBTYWx0ZWRfX1umxqtkw/Nzo 9+M4MmORbrfdu2u0DC+d8SXjPKoZS1175aVh7DBY1/a27lWWbh9G1+XKvp3wAz5zMiLy8yWm7fa UJCm6RXQMzTkb0K+Pik/IAQotnGABns= X-Proofpoint-ORIG-GUID: 8unbbFT5SddJXJJPJZJ4TNG9UItmnBVz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDIwMCBTYWx0ZWRfX0P1rHXIM4cT8 b2q525OpbFeq/QnkhBmpAvfh9va/zidJtcLNZ9Up3wcyr36NNO72DwoaSy40be/G2oU4xfVYUT6 J4BUbKBoFk3cFf7Shdw2cZhSlH7WlmYbeIHINVpGuvT+ogQLA+IyCh+E8ACDD08+nwML8gPDZZA zm7V8y/S8XJTLP2bpW7pOloDklaI65uDLQBt7rHYBN3aOvSXqgDbVwMDMZ45b9mmH9XOUYdAySW ZtLqflm73aeRWwPH4HzK2VOgaMluKXDbhV8Z/FSFn9kZzUD1Vc5Z03qtog/KQPd4rtxSUhfzwEv zTcpggYXTP2mIf6QKTFR3Et23ZnG1WcEeuCTw1sfCfXgDt3VmdJUpEyKH0QcCC/AC5jjY2cQy74 amPs2tFK6IJUwDgA2UX86jC2gszWS8C3vA9/DEn1TJDFQ9eJqTELZO2/tgDnY03udYrBLmjn89K exzCD4NVvNCt8PNfxqw== X-Authority-Analysis: v=2.4 cv=BswIUoX5 c=1 sm=1 tr=0 ts=6aa94ca9 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=5oCPkDSuF8hkarQvZ6UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_04,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 spamscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150200 On 8/28/2026 5:32 AM, Andi Shyti wrote: > Hi Viken, > > On Thu, Aug 27, 2026 at 06:44:21PM +0530, Viken Dadhaniya wrote: >> On 8/26/2026 7:27 PM, Andi Shyti wrote: >>> ... >>> >>>> +static void qcom_i2c_target_hw_reset(struct qcom_i2c_target *target) >>>> +{ >>>> + /* Clear error bits before SW_RESET; the reset may not be instantaneous */ >>>> + writel(BIT(ERR_CONDITION) | BIT(CLOCK_LOW_TIMEOUT), >>>> + target->base + I2C_S_IRQ_CLR); >>>> + writel(SW_RESET, target->base + I2C_S_SW_RESET_REG); >>>> + /* >>>> + * I2C_S_SW_RESET_REG is write-only so completion cannot be polled. >>>> + * Use a conservative delay to allow the reset to finish before >>>> + * reconfiguring the controller. >>>> + */ >>>> + usleep_range(10, 20); >>> >>> This is also called in atomic context from the irq handler. >>> Please avoid using usleep_range(), perhaps you can put this in a >>> thread. >>> >> >> Thanks for the review. The delay is only 20 µs, so we were >> thinking of replacing usleep_range() with udelay() instead of >> converting to a threaded IRQ, to avoid the added complexity on >> all the normal fast paths. > > perhaps before sleeping you could check the context you are > executing (with an explaining comment). This helper is reached from the hard IRQ error handler, so it must remain atomic-safe regardless of the current context. Since the reset wait is only 20 µs, I will replace usleep_range() with udelay() and add a comment explaining why a non-sleeping delay is required. > > Thanks, > Andi