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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952df3c7sm15264123f8f.40.2025.10.27.10.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 10:58:42 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mark Brown , Vinod Koul , Chen-Yu Tsai Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-sunxi@lists.linux.dev, linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 09/10] arm64: dts: allwinner: a523: Add SPDIF TX pin on PB and PI pins Date: Mon, 27 Oct 2025 18:58:41 +0100 Message-ID: <4686611.LvFx2qVVIh@jernej-laptop> In-Reply-To: <20251027125655.793277-10-wens@kernel.org> References: <20251027125655.793277-1-wens@kernel.org> <20251027125655.793277-10-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 27. oktober 2025 ob 13:56:50 Srednjeevropski standardni =C4= =8Das je Chen-Yu Tsai napisal(a): > The SPDIF TX (called OWA OUT in the datasheet) is available on three > pins. Of those, the PH pin is unlikely to be used since it conflicts > with the first Ethernet controller. >=20 > The Radxa Cubie A5E exposes SPDIF TX through the PI pin group on the > 40-pin GPIO header. >=20 > The Orange Pi 4A exposes SPDIF TX through both the PB and PI pin > groups on the 40-pin GPIO header. The PB pin alternatively would be > used for I2S0 though. >=20 > Add pinmux settings for both options so potential users can directly > reference either one. >=20 > Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec Best regards, Jernej