From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbdASKYX (ORCPT ); Thu, 19 Jan 2017 05:24:23 -0500 Received: from mga01.intel.com ([192.55.52.88]:61136 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751558AbdASKYV (ORCPT ); Thu, 19 Jan 2017 05:24:21 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,253,1477983600"; d="scan'208";a="810758627" Subject: Re: [RESEND PATCHv1 7/8] mmc: sdhci-msm: Make HS400 tuning follow as per recommeneded HW sequence To: Ritesh Harjani , ulf.hansson@linaro.org References: <1484031652-12059-1-git-send-email-riteshh@codeaurora.org> <1484031652-12059-8-git-send-email-riteshh@codeaurora.org> Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, asutoshd@codeaurora.org, stummala@codeaurora.org, venkatg@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, git@kchr.de From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <468b4540-d64d-8ce6-03a4-33304fdd5413@intel.com> Date: Thu, 19 Jan 2017 12:15:56 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1484031652-12059-8-git-send-email-riteshh@codeaurora.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/01/17 09:00, Ritesh Harjani wrote: > During tuning execution for HS400 mode, HW sequence recommends > to select MCLK_SEL/2(0x3) in VENDOR_SPEC & sdhc msm clock at GCC > to be 400MHZ (nearest supported clk). Add this change in tuning > sequence during HS400 tuning. > > Signed-off-by: Ritesh Harjani You may need to re-base this if you make changes as per patch 6, but otherwise: Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-msm.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index 84d29dd..fa9bce3 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -151,7 +151,8 @@ static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, > */ > if (ios.timing == MMC_TIMING_UHS_DDR50 || > ios.timing == MMC_TIMING_MMC_DDR52 || > - ios.timing == MMC_TIMING_MMC_HS400) > + ios.timing == MMC_TIMING_MMC_HS400 || > + host->flags & SDHCI_HS400_TUNING) > clock *= 2; > return clock; > } > @@ -611,7 +612,8 @@ void sdhci_msm_hc_select_mode(struct sdhci_host *host) > { > struct mmc_ios ios = host->mmc->ios; > > - if (ios.timing == MMC_TIMING_MMC_HS400) > + if (ios.timing == MMC_TIMING_MMC_HS400 || > + host->flags & SDHCI_HS400_TUNING) > msm_hc_select_hs400(host); > else > msm_hc_select_default(host); > @@ -831,6 +833,16 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) > ios.timing == MMC_TIMING_UHS_SDR104)) > return 0; > > + /* > + * For HS400 tuning in HS200 timing requires: > + * - select MCLK/2 in VENDOR_SPEC > + * - program MCLK to 400MHz (or nearest supported) in GCC > + */ > + if (host->flags & SDHCI_HS400_TUNING) { > + sdhci_msm_hc_select_mode(host); > + msm_set_clock_rate_for_bus_mode(host, ios.clock); > + } > + > retry: > /* First of all reset the tuning block */ > rc = msm_init_cm_dll(host); >