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([2a02:810d:15c0:828:d0d5:7818:2f46:5e76]) by smtp.gmail.com with ESMTPSA id h10-20020a1709070b0a00b00965ac1510f8sm901598ejl.185.2023.05.08.23.39.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 23:39:26 -0700 (PDT) Message-ID: <46b0dbd4-5695-1a2d-8d06-0a60a7c3a151@linaro.org> Date: Tue, 9 May 2023 08:39:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH] arm64: defconfig: enable PCIe controller on TI platforms Content-Language: en-US To: Achal Verma , Catalin Marinas , Will Deacon , Bjorn Andersson , Arnd Bergmann , Geert Uytterhoeven , Konrad Dybcio , "N_colas F . R . A . Prado" , Mark Brown , Rafa_ Mi_ecki , Vignesh Raghavendra , Nishanth Menon , Milind Parab , Swapnil Kashinath Jakhade Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230509063431.1203367-1-a-verma1@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20230509063431.1203367-1-a-verma1@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/05/2023 08:34, Achal Verma wrote: > Enable PCIe controller and serdes drivers to enable PCIe functionality. > * Enable Cadence serdes phy and wrapper driver. > * Enable Cadence PCIe controller driver. Why? IOW, which boards needs it? > > Signed-off-by: Achal Verma > --- > arch/arm64/configs/defconfig | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index a24609e14d50..ff187dd585c2 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -230,9 +230,16 @@ CONFIG_PCIE_HISI_STB=y > CONFIG_PCIE_TEGRA194_HOST=m > CONFIG_PCIE_VISCONTI_HOST=y > CONFIG_PCIE_LAYERSCAPE_GEN4=y > +CONFIG_PCIE_CADENCE=y =m > +CONFIG_PCIE_CADENCE_HOST=y > +CONFIG_PCIE_CADENCE_EP=y > +CONFIG_PCI_J721E=y =m > +CONFIG_PCI_J721E_HOST=y > +CONFIG_PCI_J721E_EP=y > CONFIG_PCI_ENDPOINT=y > CONFIG_PCI_ENDPOINT_CONFIGFS=y > CONFIG_PCI_EPF_TEST=m > +CONFIG_PCI_EPF_NTB=m > CONFIG_DEVTMPFS=y > CONFIG_DEVTMPFS_MOUNT=y > CONFIG_FW_LOADER_USER_HELPER=y > @@ -1330,8 +1337,8 @@ CONFIG_RESET_TI_SCI=y > CONFIG_PHY_XGENE=y > CONFIG_PHY_CAN_TRANSCEIVER=m > CONFIG_PHY_SUN4I_USB=y > -CONFIG_PHY_CADENCE_TORRENT=m > -CONFIG_PHY_CADENCE_SIERRA=m > +CONFIG_PHY_CADENCE_TORRENT=y > +CONFIG_PHY_CADENCE_SIERRA=y Why? Commit msg does not explain it. > CONFIG_PHY_MIXEL_MIPI_DPHY=m > CONFIG_PHY_FSL_IMX8M_PCIE=y > CONFIG_PHY_HI6220_USB=y > @@ -1363,8 +1370,8 @@ CONFIG_PHY_SAMSUNG_UFS=y > CONFIG_PHY_UNIPHIER_USB2=y > CONFIG_PHY_UNIPHIER_USB3=y > CONFIG_PHY_TEGRA_XUSB=y > -CONFIG_PHY_AM654_SERDES=m > -CONFIG_PHY_J721E_WIZ=m > +CONFIG_PHY_AM654_SERDES=y > +CONFIG_PHY_J721E_WIZ=y Why? > CONFIG_ARM_CCI_PMU=m > CONFIG_ARM_CCN=m > CONFIG_ARM_CMN=m Best regards, Krzysztof