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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac23973af6fsm899839366b.100.2025.03.11.02.49.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Mar 2025 02:49:18 -0700 (PDT) Message-ID: <46b6dbf4-0d2d-4165-8657-7bd8a1329d61@linaro.org> Date: Tue, 11 Mar 2025 09:49:16 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/8] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue References: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> <20250306-videocc-pll-multi-pd-voting-v2-1-0cd00612bc0e@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250306-videocc-pll-multi-pd-voting-v2-1-0cd00612bc0e@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 06/03/2025 08:55, Jagadeesh Kona wrote: > To configure the video PLLs and enable the video GDSCs on SM8450, > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along > with MMCX. Therefore, update the videocc bindings to include > the MXC power domain on these platforms. > > Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") > Signed-off-by: Jagadeesh Kona > Reviewed-by: Bryan O'Donoghue > Acked-by: Rob Herring (Arm) > --- > Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -32,9 +32,11 @@ properties: > - description: Video AHB clock from GCC > > power-domains: > - maxItems: 1 > description: > - MMCX power domain. > + Power domains required for the clock controller to operate > + items: > + - description: MMCX power domain > + - description: MXC power domain > > required-opps: > maxItems: 1 > @@ -72,7 +74,8 @@ examples: > reg = <0x0aaf0000 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > required-opps = <&rpmhpd_opp_low_svs>; > #clock-cells = <1>; > #reset-cells = <1>; > > -- > 2.34.1 > > The ordering of these patches is a bit weird with this binding first and then the rest of the bindings later. Also switched my linux-arm-msm email recently so only got the first patch with my RB in my Linaro inbox. Suggest as standard practice when you get review feedback to CC previous reviewers on all patches in subsequent series, especially if you are picking up an RB on one of those patches. TL;DR please cc me on V3. --- bod