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[93.144.65.244]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4602cda3651sm39503219f8f.32.2026.06.08.03.09.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 03:09:43 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v4 06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe Date: Mon, 8 Jun 2026 12:09:24 +0200 Message-ID: <46f059124fc039b83ff3b8d9efb2fe3da55dc7ac.1780912893.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board. Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input. Signed-off-by: Stefano Radaelli --- v3->v4: - Add pcie reset-gpios instead of deprecated one v2->v3: - v1->v2: - Adjust PCIe controller configuration .../dts/freescale/imx8mp-var-som-symphony.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 34a956c98635..a2becf5409cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,12 @@ led-0 { }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -146,6 +152,18 @@ rtc@68 { }; }; +&pcie { + reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; -- 2.47.3