From: Alessio Belle <Alessio.Belle@imgtec.com>
To: Alexandru Dadu <Alexandru.Dadu@imgtec.com>
Cc: Luigi Santivetti <Luigi.Santivetti@imgtec.com>,
"tzimmermann@suse.de" <tzimmermann@suse.de>,
"imagination@lists.freedesktop.org"
<imagination@lists.freedesktop.org>,
"simona@ffwll.ch" <simona@ffwll.ch>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"airlied@gmail.com" <airlied@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"maarten.lankhorst@linux.intel.com"
<maarten.lankhorst@linux.intel.com>,
"mripard@kernel.org" <mripard@kernel.org>
Subject: Re: [PATCH v4 1/5] drm/imagination: Prepare heap config header for multi-arch support
Date: Fri, 6 Nov 2026 09:26:45 +0000 [thread overview]
Message-ID: <470b9ade05fe06c28195c6511d2dca9ef053970a.camel@imgtec.com> (raw)
In-Reply-To: <20261103-prep-meta-fw-arch-independent-v4-1-513d1c51f458@imgtec.com>
On Tue, 2026-11-03 at 11:00 +0200, Alexandru Dadu wrote:
> Update the name of pvr_rogue_heap_config.h to pvr_heap_config.h to
> prepare it for a more generic implementation that will have memory
> sections defined for multiple GPU architectures.
> Update the multi-arch common define names to a generic format.
>
> Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
Reviewed-by: Alessio Belle <alessio.belle@imgtec.com>
This isn't really related to the rest and could be applied by itself, or split
if you need to send a v5 and this hasn't been applied yet.
Thanks,
Alessio
> ---
> drivers/gpu/drm/imagination/pvr_fw.c | 7 +++---
> drivers/gpu/drm/imagination/pvr_gem.h | 2 +-
> .../{pvr_rogue_heap_config.h => pvr_heap_config.h} | 26 +++++++++++-----------
> drivers/gpu/drm/imagination/pvr_vm.c | 18 +++++++--------
> 4 files changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c
> index c6c77b152342..4d5df5272f46 100644
> --- a/drivers/gpu/drm/imagination/pvr_fw.c
> +++ b/drivers/gpu/drm/imagination/pvr_fw.c
> @@ -9,9 +9,8 @@
> #include "pvr_fw_startstop.h"
> #include "pvr_fw_trace.h"
> #include "pvr_gem.h"
> +#include "pvr_heap_config.h"
> #include "pvr_power.h"
> -#include "pvr_rogue_fwif_dev_info.h"
> -#include "pvr_rogue_heap_config.h"
> #include "pvr_vm.h"
>
> #include <drm/drm_drv.h>
> @@ -372,8 +371,8 @@ fw_sysinit_init(void *cpu_ptr, void *priv)
> WARN_ON(pvr_fw_object_get_dma_addr(fw_mem->fault_page_obj, 0, &fault_dma_addr));
> fwif_sysinit->fault_phys_addr = (u64)fault_dma_addr;
>
> - fwif_sysinit->pds_exec_base = ROGUE_PDSCODEDATA_HEAP_BASE;
> - fwif_sysinit->usc_exec_base = ROGUE_USCCODE_HEAP_BASE;
> + fwif_sysinit->pds_exec_base = PVR_PDSCODEDATA_HEAP_BASE;
> + fwif_sysinit->usc_exec_base = PVR_USCCODE_HEAP_BASE;
>
> pvr_fw_object_get_fw_addr(fw_mem->runtime_cfg_obj, &fwif_sysinit->runtime_cfg_fw_addr);
> pvr_fw_object_get_fw_addr(fw_dev->fw_trace.tracebuf_ctrl_obj,
> diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
> index 4286e047ae24..ae7af82b6f17 100644
> --- a/drivers/gpu/drm/imagination/pvr_gem.h
> +++ b/drivers/gpu/drm/imagination/pvr_gem.h
> @@ -4,7 +4,7 @@
> #ifndef PVR_GEM_H
> #define PVR_GEM_H
>
> -#include "pvr_rogue_heap_config.h"
> +#include "pvr_heap_config.h"
> #include "pvr_rogue_meta.h"
>
> #include <uapi/drm/pvr_drm.h>
> diff --git a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h b/drivers/gpu/drm/imagination/pvr_heap_config.h
> similarity index 85%
> rename from drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
> rename to drivers/gpu/drm/imagination/pvr_heap_config.h
> index 5c33b342dda5..280bf1ed523b 100644
> --- a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
> +++ b/drivers/gpu/drm/imagination/pvr_heap_config.h
> @@ -1,8 +1,8 @@
> /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> /* Copyright (c) 2023 Imagination Technologies Ltd. */
>
> -#ifndef PVR_ROGUE_HEAP_CONFIG_H
> -#define PVR_ROGUE_HEAP_CONFIG_H
> +#ifndef PVR_HEAP_CONFIG_H
> +#define PVR_HEAP_CONFIG_H
>
> #include <linux/sizes.h>
>
> @@ -14,7 +14,7 @@
> * fits into this, but the firmware heap is only ever created in the
> * kernel driver and never exposed to userspace.
> *
> - * ROGUE_PDSCODEDATA_HEAP_BASE and ROGUE_USCCODE_HEAP_BASE will be programmed,
> + * PVR_PDSCODEDATA_HEAP_BASE and PVR_USCCODE_HEAP_BASE will be programmed,
> * on a global basis, into ROGUE_CR_PDS_EXEC_BASE and ROGUE_CR_USC_CODE_BASE_*
> * respectively. Therefore if client drivers use multiple configs they must
> * still be consistent with their definitions for these heaps.
> @@ -38,9 +38,9 @@
> /* 0x80_0000_0000 ************************************************************/
>
> /* 0x80_0000_0000 - 0x9F_FFFF_FFFF **/
> -/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP */
> -#define ROGUE_GENERAL_HEAP_BASE 0x8000000000ull
> -#define ROGUE_GENERAL_HEAP_SIZE SZ_128G
> +/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP **/
> +#define PVR_GENERAL_HEAP_BASE 0x8000000000ull
> +#define PVR_GENERAL_HEAP_SIZE SZ_128G
>
> /* 0xA0_0000_0000 - 0xAF_FFFF_FFFF */
> /* 640 GiB to 704 GiB, size of 64 GiB : FREE */
> @@ -58,8 +58,8 @@
>
> /* 0xDA_0000_0000 - 0xDA_FFFF_FFFF */
> /* 872 GiB to 876 GiB, size of 4 GiB : PDSCODEDATA_HEAP */
> -#define ROGUE_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
> -#define ROGUE_PDSCODEDATA_HEAP_SIZE SZ_4G
> +#define PVR_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
> +#define PVR_PDSCODEDATA_HEAP_SIZE SZ_4G
>
> /* 0xDB_0000_0000 - 0xDB_FFFF_FFFF */
> /* 876 GiB to 880 GiB, size of 256 MiB (reserved 4GiB) : BRN */
> @@ -76,8 +76,8 @@
>
> /* 0xE0_0000_0000 - 0xE0_FFFF_FFFF */
> /* 896 GiB to 900 GiB, size of 4 GiB : USCCODE_HEAP */
> -#define ROGUE_USCCODE_HEAP_BASE 0xE000000000ull
> -#define ROGUE_USCCODE_HEAP_SIZE SZ_4G
> +#define PVR_USCCODE_HEAP_BASE 0xE000000000ull
> +#define PVR_USCCODE_HEAP_SIZE SZ_4G
>
> /* 0xE1_0000_0000 - 0xE1_BFFF_FFFF */
> /* 900 GiB to 903 GiB, size of 3 GiB : RESERVED */
> @@ -99,8 +99,8 @@
>
> /* 0xF2_0000_0000 - 0xF2_001F_FFFF **/
> /* 968 GiB to 969 GiB, size of 2 MiB : VISTEST_HEAP */
> -#define ROGUE_VISTEST_HEAP_BASE 0xF200000000ull
> -#define ROGUE_VISTEST_HEAP_SIZE SZ_2M
> +#define PVR_VISTEST_HEAP_BASE 0xF200000000ull
> +#define PVR_VISTEST_HEAP_SIZE SZ_2M
>
> /* 0xF2_4000_0000 - 0xF2_FFFF_FFFF */
> /* 969 GiB to 972 GiB, size of 3 GiB : FREE */
> @@ -110,4 +110,4 @@
>
> /* 0xFF_FFFF_FFFF ************************************************************/
>
> -#endif /* PVR_ROGUE_HEAP_CONFIG_H */
> +#endif /* PVR_HEAP_CONFIG_H */
> diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagination/pvr_vm.c
> index ceb78694cd98..ae965043237d 100644
> --- a/drivers/gpu/drm/imagination/pvr_vm.c
> +++ b/drivers/gpu/drm/imagination/pvr_vm.c
> @@ -6,9 +6,9 @@
> #include "pvr_device.h"
> #include "pvr_drv.h"
> #include "pvr_gem.h"
> +#include "pvr_heap_config.h"
> #include "pvr_mmu.h"
> #include "pvr_rogue_fwif.h"
> -#include "pvr_rogue_heap_config.h"
>
> #include <drm/drm_exec.h>
> #include <drm/drm_gem.h>
> @@ -950,20 +950,20 @@ static const struct drm_pvr_static_data_area static_data_areas[] = {
> */
> static const struct drm_pvr_heap pvr_heaps[] = {
> [DRM_PVR_HEAP_GENERAL] = {
> - .base = ROGUE_GENERAL_HEAP_BASE,
> - .size = ROGUE_GENERAL_HEAP_SIZE,
> + .base = PVR_GENERAL_HEAP_BASE,
> + .size = PVR_GENERAL_HEAP_SIZE,
> .flags = 0,
> .page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
> },
> [DRM_PVR_HEAP_PDS_CODE_DATA] = {
> - .base = ROGUE_PDSCODEDATA_HEAP_BASE,
> - .size = ROGUE_PDSCODEDATA_HEAP_SIZE,
> + .base = PVR_PDSCODEDATA_HEAP_BASE,
> + .size = PVR_PDSCODEDATA_HEAP_SIZE,
> .flags = 0,
> .page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
> },
> [DRM_PVR_HEAP_USC_CODE] = {
> - .base = ROGUE_USCCODE_HEAP_BASE,
> - .size = ROGUE_USCCODE_HEAP_SIZE,
> + .base = PVR_USCCODE_HEAP_BASE,
> + .size = PVR_USCCODE_HEAP_SIZE,
> .flags = 0,
> .page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
> },
> @@ -974,8 +974,8 @@ static const struct drm_pvr_heap pvr_heaps[] = {
> .page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
> },
> [DRM_PVR_HEAP_VIS_TEST] = {
> - .base = ROGUE_VISTEST_HEAP_BASE,
> - .size = ROGUE_VISTEST_HEAP_SIZE,
> + .base = PVR_VISTEST_HEAP_BASE,
> + .size = PVR_VISTEST_HEAP_SIZE,
> .flags = 0,
> .page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
> },
>
next prev parent reply other threads:[~2026-11-06 9:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 9:00 [PATCH v4 0/5] drm/imagination: RISC-V and META firmware interface updates Alexandru Dadu
2026-11-03 9:00 ` [PATCH v4 1/5] drm/imagination: Prepare heap config header for multi-arch support Alexandru Dadu
2026-11-06 9:26 ` Alessio Belle [this message]
2026-11-03 9:00 ` [PATCH v4 2/5] drm/imagination: Limit access to the RISC-V firmware interface Alexandru Dadu
2026-11-03 9:00 ` [PATCH v4 3/5] drm/imagination: Make the RISC-V firmware header arch-independent Alexandru Dadu
2026-11-03 9:00 ` [PATCH v4 4/5] drm/imagination: Limit access to the META firmware interface Alexandru Dadu
2026-11-03 9:00 ` [PATCH v4 5/5] drm/imagination: Make the META firmware header arch-independent Alexandru Dadu
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