From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 423FCC74A5B for ; Thu, 23 Mar 2023 22:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231452AbjCWWu0 (ORCPT ); Thu, 23 Mar 2023 18:50:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229734AbjCWWuX (ORCPT ); Thu, 23 Mar 2023 18:50:23 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7B141721; Thu, 23 Mar 2023 15:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=MIME-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Iyc6uhkh5Y951Se0fV7FDZJ0/8B09t7sfOAbPMk0GYs=; b=W5qZ3xfELY6Z9Ib+tOG348nFU6 7FQMaVNo8AvoyTBa9Be7thsxBW8lwoWErl4DLQoHr1j2/NHD9rtStA88CYgkr17YBXN5qlhJLuhG3 pqhWRW/qvWn2L3EVZRkTUtznrrOqGmeKfz2rOPWcrAx/bxxBWaMi/2u+W+mToKheDbpHoDSZzf1qG AT/ec2RBc8L9kozYlPAAWd1D2hoNI7VgUvE53Ltbzl7v04EiRV9rk/XS+437MxD1LCq4obiHl2/Pf /DYn3hR5OCkME62dQoaCjzRy84mrjSKFV0OUqV3WmRD22HU8d2bHicKthPNW7Se+QWlX/pLXFsSrs Xh2mj57w==; Received: from [2001:8b0:10b:5:b3d4:e39d:531b:642a] (helo=u3832b3a9db3152.ant.amazon.com) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1pfTkc-004Kqd-Gb; Thu, 23 Mar 2023 22:49:45 +0000 Message-ID: <47150207bfb76bb98aff678cf7c91f245e9f5dd9.camel@infradead.org> Subject: Re: [PATCH v16 3/8] cpu/hotplug: Add dynamic parallel bringup states before CPUHP_BRINGUP_CPU From: David Woodhouse To: Thomas Gleixner , Usama Arif , kim.phillips@amd.com, brgerst@gmail.com Cc: piotrgorski@cachyos.org, oleksandr@natalenko.name, arjan@linux.intel.com, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, paulmck@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com, thomas.lendacky@amd.com, seanjc@google.com, pmenzel@molgen.mpg.de, fam.zheng@bytedance.com, punit.agrawal@bytedance.com, simon.evans@bytedance.com, liangma@liangbit.com, gpiccoli@igalia.com Date: Thu, 23 Mar 2023 22:49:40 +0000 In-Reply-To: <874jqb8588.ffs@tglx> References: <20230321194008.785922-1-usama.arif@bytedance.com> <20230321194008.785922-4-usama.arif@bytedance.com> <874jqb8588.ffs@tglx> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/pkcs7-signature"; boundary="=-71vH2AL2r3jcGL6hBE+E" User-Agent: Evolution 3.44.4-0ubuntu1 MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by casper.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-71vH2AL2r3jcGL6hBE+E Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2023-03-23 at 23:36 +0100, Thomas Gleixner wrote: > On Tue, Mar 21 2023 at 19:40, Usama Arif wrote: > > =C2=A0void bringup_nonboot_cpus(unsigned int setup_max_cpus) > > =C2=A0{ > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned int n =3D setup_max= _cpus - num_online_cpus(); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned int cpu; > > =C2=A0 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * An architecture may have = registered parallel pre-bringup states to > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * which each CPU may be bro= ught in parallel. For each such state, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * bring N CPUs to it in tur= n before the final round of bringing them > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * online. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (n > 0) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0enum cpuhp_state st =3D CPUHP_BP_PARALLEL_DYN; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0while (st <=3D CPUHP_BP_PARALLEL_DYN_END && cpuhp_hp_s= tates[st].name) { >=20 >=20 > There is no point in special casing this. All architectures can invoke > the CPUHP_BP_* states before CPUHP_BRINGUP_CPU for each to be brought up > CPU first. So this can be made unconditional and common exercised code. >=20 There were three paragraphs in the commit message explaining why I didn't want to do that. It didn't work for x86 before I started, and I haven't reviewed *every* other architecture to ensure that it will work there. It was opt-in for a reason. :) > Aside of that this dynamic state range is pretty pointless. There is > really nothing dynamic here and there is no real good reason to have > four dynamic parallel states just because. The original patch set did use more than one state; the plan to do microcode updates in parallel does involve doing at least one more, I believe. =20 https://lore.kernel.org/all/eb6717dfc4ceb99803c0396f950db7c3231c75ef.camel@= infradead.org/ > The only interesting thing after CPUHP_BP_PREPARE_DYN_END and before > CPUHP_BP_BRINGUP is a state which kicks the AP into life, i.e. we can > just hardcode that as CPUHP_BP_PARALLEL_STARTUP. >=20 > Thanks, >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tglx > --- > --- a/include/linux/cpuhotplug.h > +++ b/include/linux/cpuhotplug.h > @@ -133,6 +133,20 @@ enum cpuhp_state { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUHP_MIPS_SOC_PREPARE, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUHP_BP_PREPARE_DYN, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUHP_BP_PREPARE_DYN_END= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=3D CPUHP_BP_PREPARE_DYN + 20, > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * This is an optional state i= f the architecture supports parallel > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * startup. It's used to send = the startup IPI so that the APs can > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * run in parallel through the= low level startup code instead of > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * sending the IPIs one by one= in CPUHP_BRINGUP_CPU. This avoids > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * waiting for the AP to react= and shortens the serialized bringup. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUHP_BP_PARALLEL_STARTUP, > + > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Fully per AP serialized bri= ngup from here on. If the > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * architecture does no regist= er the CPUHP_BP_PARALLEL_STARTUP > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * state, this step sends the = startup IPI first. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ Not sure I'd conceded that yet; the APs do their *own* bringup from here, and that really ought to be able to run in parallel. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CPUHP_BRINGUP_CPU, > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* --=-71vH2AL2r3jcGL6hBE+E Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEkQw ggYQMIID+KADAgECAhBNlCwQ1DvglAnFgS06KwZPMA0GCSqGSIb3DQEBDAUAMIGIMQswCQYDVQQG EwJVUzETMBEGA1UECBMKTmV3IEplcnNleTEUMBIGA1UEBxMLSmVyc2V5IENpdHkxHjAcBgNVBAoT FVRoZSBVU0VSVFJVU1QgTmV0d29yazEuMCwGA1UEAxMlVVNFUlRydXN0IFJTQSBDZXJ0aWZpY2F0 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