From: <Conor.Dooley@microchip.com>
To: <sudeep.holla@arm.com>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<palmer@rivosinc.com>, <aou@eecs.berkeley.edu>,
<catalin.marinas@arm.com>, <will@kernel.org>,
<gregkh@linuxfoundation.org>, <rafael@kernel.org>,
<Daire.McNamara@microchip.com>, <Conor.Dooley@microchip.com>,
<niklas.cassel@wdc.com>, <damien.lemoal@opensource.wdc.com>,
<geert@linux-m68k.org>, <zong.li@sifive.com>, <kernel@esmil.dk>,
<hahnjo@hahnjo.de>, <guoren@kernel.org>, <anup@brainfault.org>,
<atishp@atishpatra.org>, <changbin.du@intel.com>,
<heiko@sntech.de>, <philipp.tomsich@vrull.eu>, <robh@kernel.org>,
<maz@kernel.org>, <viresh.kumar@linaro.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <Brice.Goglin@inria.fr>
Subject: Re: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology()
Date: Fri, 8 Jul 2022 08:35:57 +0000 [thread overview]
Message-ID: <473e6b17-465b-3d14-b04d-01b187390e66@microchip.com> (raw)
In-Reply-To: <20220708082443.azoqvuj7afrg7ox7@bogus>
On 08/07/2022 09:24, Sudeep Holla wrote:
> On Thu, Jul 07, 2022 at 11:04:35PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> RISC-V & arm64 both use an almost identical method of filling in
>> default vales for arch topology. Create a weakly defined default
>> implementation with the intent of migrating both archs to use it.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> drivers/base/arch_topology.c | 19 +++++++++++++++++++
>> include/linux/arch_topology.h | 1 +
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
>> index 441e14ac33a4..07e84c6ac5c2 100644
>> --- a/drivers/base/arch_topology.c
>> +++ b/drivers/base/arch_topology.c
>> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
>> }
>> }
>>
>> +void __weak store_cpu_topology(unsigned int cpuid)
Does using __weak here make sense to you?
>
> I prefer to have this as default implementation. So just get the risc-v
> one pushed to upstream first(for v5.20) and get all the backports if required.
> Next cycle(i.e. v5.21), you can move both RISC-V and arm64.
>
Yeah, that was my intention. I meant to label patch 1/4 as "PATCH"
and (2,3,4)/4 as RFC but forgot. I talked with Palmer about doing
the risc-v impl. and then migrate both on IRC & he seemed happy with
it.
If you're okay with patch 1/4, I'll resubmit it as a standalone v2.
Thanks,
Conor.
next prev parent reply other threads:[~2022-07-08 8:36 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-07 22:04 [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor Dooley
2022-07-07 22:04 ` [RFC 1/4] riscv: arch-topology: fix default topology reporting Conor Dooley
2022-07-07 22:04 ` [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology() Conor Dooley
2022-07-08 8:24 ` Sudeep Holla
2022-07-08 8:35 ` Conor.Dooley [this message]
2022-07-08 9:21 ` Sudeep Holla
2022-07-08 9:28 ` Geert Uytterhoeven
2022-07-08 9:47 ` Sudeep Holla
2022-07-08 10:03 ` Greg KH
2022-07-08 11:39 ` Sudeep Holla
2022-07-08 11:57 ` Conor.Dooley
2022-07-08 13:59 ` Sudeep Holla
2022-07-08 10:02 ` Conor.Dooley
2022-07-07 22:04 ` [RFC 3/4] riscv: arch-topology: move riscv to the generic store_cpu_topology() Conor Dooley
2022-07-07 22:04 ` [RFC 4/4] arm64: arch-topology move arm64 " Conor Dooley
2022-07-07 22:06 ` [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor.Dooley
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