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Wed, 29 Jan 2025 18:43:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50TIhSFn017246 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jan 2025 18:43:28 GMT Received: from [10.71.108.79] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 29 Jan 2025 10:43:28 -0800 Message-ID: <4761c8ad-6f02-45bf-8fc1-87e40b7702fe@quicinc.com> Date: Wed, 29 Jan 2025 10:43:21 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent To: Krzysztof Kozlowski , Bjorn Andersson , Michael Turquette , Stephen Boyd , , , References: <20250129154519.209791-1-krzysztof.kozlowski@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20250129154519.209791-1-krzysztof.kozlowski@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HoxU2DFGhxenA6KQ85beXwYbRfTUj1mj X-Proofpoint-ORIG-GUID: HoxU2DFGhxenA6KQ85beXwYbRfTUj1mj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-29_04,2025-01-29_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=896 impostorscore=0 suspectscore=0 clxscore=1011 mlxscore=0 malwarescore=0 priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501290146 On 1/29/2025 7:45 AM, Krzysztof Kozlowski wrote: > The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up > the rates, because this messes up entire clock hierarchy when setting > clock rates in MSM DSI driver. > > The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates > via dev_pm_opp_set_rate() on byte clock and then sets individual clock > rates, like pixel and byte_intf clocks, to proper frequencies. Having > CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte > clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this > and align with SM8550 and SM8650. > > Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller") > Signed-off-by: Krzysztof Kozlowski > > --- > > Fix for v6.14-rcX. > --- > drivers/clk/qcom/dispcc-sm8750.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c > index 0358dff91da5..e9bca179998b 100644 > --- a/drivers/clk/qcom/dispcc-sm8750.c > +++ b/drivers/clk/qcom/dispcc-sm8750.c > @@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { > &disp_cc_mdss_byte0_clk_src.clkr.hw, > }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT, > .ops = &clk_regmap_div_ops, > }, > }; > @@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { > &disp_cc_mdss_byte1_clk_src.clkr.hw, > }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT, > .ops = &clk_regmap_div_ops, > }, > }; Reviewed-by: Abhinav Kumar