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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDA5NyBTYWx0ZWRfXzHtJE5uOqtcr 8qAjyi3DcFdgUlwHdCZ+23m9uxo/V09o3mvXDycjtLo4rNao5CovO8bG5g302yGocYeIASX3Gr3 VweEAGmRZuZJOW2ecEQZHeYW04VJSrQ= X-Authority-Analysis: v=2.4 cv=cuGrVV4i c=1 sm=1 tr=0 ts=6a575a10 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=Cs3LUSVxlKGBK3EvLigA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: b7ozyE1RMeB2OXuBWba1OGlyWyvrjya- X-Proofpoint-GUID: b7ozyE1RMeB2OXuBWba1OGlyWyvrjya- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDA5NyBTYWx0ZWRfX+OXXXmrs8BOu T9Rz8AOem+GEufyPNEGnNXbJIXi+yPYp7kPbwiA3nU9c4Z4z7bHln1sIQawUqkdLAb9xcusDYOp 8zxSwnWTmmm3vz+unqO0FO3bfHwY6Ty5txmQhEF+dEq6ZOePNLPgiREDPi50x2W4HI5OuAwgbsV WsvxsGc2XNYPjg1zz81aNy4ist3haf3ZmaooSXVP0fshFDNQLciTaB7D+YofH5w0lvDZc7f4oD+ ibkmV8girbj+QGq/fB+ufLAmM2D5LZWEljkMiVokbjEoEZAi1EoK+ckSyEPjTrFUeh9GAspvkwv hNDJ/a11LMLcgyxRkFNq902e7RLuWAcZopdk0WNYCVP4qSXhaqxjjDvI4RJCIcJx5fvPfunODDp ijyocYI1zlZPo/IXb/k7PYUAWt+tQiO/B0TS+12jYFxg1IazM0pLBnC7K7PFI5bShNh881o8obl r5NEmL8tdofc2tZDfsw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150097 On 7/13/26 12:25 PM, Sneh Mankad wrote: > The vMPM layout starts with two timer registers followed by pin register > banks (ENABLE/FALLING/RISING/POLARITY/STATUS), each with reg_stride > number of entries. > > Use qcom_mpm_offset() as the common addressing helper for both timer and > pin register accesses based on that layout. > > vMPM has MPM_REG_* values represented as contiguous register IDs, > hence replace the macros with enum qcom_mpm_reg and modify the accessor > helpers accordingly. > > Signed-off-by: Sneh Mankad > --- [...] > +static unsigned int qcom_mpm_offset(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, > + unsigned int index) > +{ > + unsigned int reg_offset; > + > + /* > + * Per the vMPM register map, TIMER[0..1] starts at register index 0 and all pin-specific > + * registers start after the two TIMER regs. Pin-specific register IDs start at > + * MPM_REG_ENABLE, so subtract it to convert to a zero-based pin-register group index. > + */ > + if (reg == MPM_REG_TIMER) > + reg_offset = index; > + else > + reg_offset = MPM_TIMER_REGS + > + (reg - MPM_REG_ENABLE) * priv->reg_stride + index; > + > + return reg_offset * sizeof(u32); I think this comment is superfluous given the visual representation of the register space just a couple dozen lines above Maybe this could be a little easier to follow written this way: s/MPM_TIMER_REGS/MPM_NUM_TIMER_REGS reg_offset = 0; if (reg != MPM_REG_TIMER) { reg_offset += MPM_NUM_TIMER_REGS; reg_offset += (reg - MPM_REG_ENABLE) * priv->reg_stride; } reg_offset += index; Konrad