From: "Dan Gora" <dan.gora@gmail.com>
To: "Andi Kleen" <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org
Subject: Re: PCI Bursting with PIO
Date: Fri, 15 Feb 2008 09:55:24 -0800 [thread overview]
Message-ID: <4779de450802150955m17c42d96j809804c3c0b99a4@mail.gmail.com> (raw)
In-Reply-To: <p73abm21ocl.fsf@bingen.suse.de>
On Fri, Feb 15, 2008 at 2:54 AM, Andi Kleen <andi@firstfloor.org> wrote:
> "Dan Gora" <dan.gora@gmail.com> writes:
> >
> > Is there any way to get PIO
>
> I assume you really mean MMIO, not PIO. PIO would be port IO.
Sorry, I always saw it referred to as "Programmed I/O" as opposed to DMA...
> You should set the MMIO mapping to write combining using an MTRR
Sorry to be thick here, but how would I go about doing that?
> You might need to add appropiate memory barriers if you rely
> on write ordering though.
Ok, thanks for the info...
dan
next prev parent reply other threads:[~2008-02-15 17:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-02-15 3:28 Dan Gora
2008-02-15 10:54 ` Andi Kleen
2008-02-15 17:55 ` Dan Gora [this message]
2008-02-15 13:02 ` Alan Cox
2008-02-15 18:00 ` Dan Gora
2008-02-15 18:41 ` H. Peter Anvin
2008-02-15 19:00 ` Alan Cox
[not found] <fa.Mbzb1/2dWnp5V/5ElzijlkAstZU@ifi.uio.no>
2008-02-16 6:00 ` Robert Hancock
2008-02-17 4:53 ` Dan Gora
[not found] <fa.QF1nJvJhMpLvtquNDa6sbADHwhs@ifi.uio.no>
[not found] ` <fa.LrKLA2l3F3abMpHk4aDjFfwzFVI@ifi.uio.no>
[not found] ` <fa.kFanAY/O5VMnSf6YXqEyxmsR62U@ifi.uio.no>
2008-02-17 19:06 ` Robert Hancock
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