On 18-02-08 23:44, H. Peter Anvin wrote:

>>>> Rene Herman wrote:
>>>>>
>>>>> Yes, but generally not any P5+ system is going to need the PIT 
>>>>> delay in the first place meaning it just doesn't matter. There were 
>>>>> the VIA issues with the PIC but unless I missed it not with the PIT.
>>>>>
>>>>
>>>> Uhm, I'm not sure I believe that's safe.
>>>>
>>>> The PIT is particularly pissy in this case -- the semantics of the 
>>>> PIT are ill-defined if there hasn't been a PIT clock between two 
>>>> adjacent accesses, so I fully expect that there are chipsets out 
>>>> there which will do very bad things in this case.
>>>
>>> Okay. Now that they're isolated, do you have a suggestion for 
>>> {in,out}b_pit? You say a PIT clock, so do you think we can bounce of 
>>> the PIT iself in this case after all?
>>
>> Am I correct that channel 1 is never used? A simple read from 0x41?
>>
> 
> Channel 1 is available for the system.  In modern systems, it's pretty 
> much available for the OS, although that's never formally stated (in the 
> original PC, it was used for DRAM refresh.)
> 
> However, I could very easily see a chipset have issues with that kind of 
> stuff.

I couldn't really, but clean it's neither. Okay, so you just want something 
like this? This initializes loops_per_jiffy somewhat more usefully -- at a 
1G CPU for P6 and 64-bit, and tuning it down again for 386/486/586.

The values taken are for what I believe to be the fastest CPUs among the 
specific family. Alan?

386-40 and P1-233 were verified, the 486-120 value was scaled from a 486-40.

_Something_ like this would seem to be the only remaining option. It seems 
fairly unuseful to #ifdef around that switch statement for kernels without 
support for the earlier families, but if you insist...

Rene.