On 17-03-08 22:00, David Brownell wrote:

>> On 15-03-08 23:46, Lev A. Melnikovsky wrote:
>>
>>> changing the bit 5 (EHCI sleep time select:  0=1us 1=10us)
>>> of register 0x4B seems to resolve my own problem.
> 
> Note that 10 usec is the value used in the EHCI spec.
> 
> And yes, waiting only 1 usec between schedule scans is
> absolutely certain to hammer on the PCI bus quite rudely,
> preventing other devices from getting Real Work done.
> 
> Could someone put together an EHCI patch to make sure
> that bit is set on vt6212 parts?  For the VT8235 that
> register seems to be marked (in an old document someone
> forwarded to me) as "reserved, do not program"; so this
> should be specific to vt6212 EHCI.  (PCI vendor 0x1106,
> device 0x3104, revision 0x60 ... the revision being what
> says "vt6212" vs "vt8235" or "vt8237" etc.

Just something like this? Completely untested as I've not the hardware 
anymore. Googling for an old lspci, I had a revision 0x63, and Lev has a 
revision 0x65. The VT6212(L) should be 0x60+ it seems.

The "CC:" should be a "Tested-by:" if that's actually the case.

But yes, as he also asked, should this be the fix at all?

Rene.