memory-barriers.txt: cache coherency vs mmio

[Stefan Richter <stefanr@s5r6.in-berlin.de>]

The subject section in memory-barriers.txt says:

"[...] MMIO accesses may, in effect, overtake accesses to cached memory 
that were emitted earlier. A memory barrier isn't sufficient in such a 
case, but rather the cache must be flushed between the cached memory 
write and the MMIO access if the two are in any way dependent."

And the lowly driver programmer immediately asks:
How do I flush the cache?

In particular, do I have to do anyhing between

	coherent_dma_buffer->datum = something;

	writel(YOU_CAN_START_DMA_NOW, register);

Thanks,
-- 
Stefan Richter
-=====-==--- --== ==-=-
http://arcgraph.de/sr/