From: "Nazle Asmade, Muhammad Nazim Amirul" <muhammad.nazim.amirul.nazle.asmade@altera.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
"dinguyen@kernel.org" <dinguyen@kernel.org>
Cc: "robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
Date: Thu, 4 Jun 2026 10:55:29 +0000 [thread overview]
Message-ID: <47a7cb44-416b-4e48-a7f2-b6b69b71896a@altera.com> (raw)
In-Reply-To: <c1aad046-fef0-4c2a-9e51-59e643e7966d@kernel.org>
On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote:
> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> Enable the SMMU on the SoCFPGA board device trees where it was
>> missing. The SoC uses a different memory-mapped base address for
>> its peripherals, which requires the System Memory Management Unit
>> (SMMU) to be active so that the Secure Device Manager (SDM) can
>> correctly access those regions through address translation.
>>
>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>> ---
>> Changes in v2:
>> - Move SMMU enable into the base DTSI file instead of individual DTS files
>>
>> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index b06c6d5d60ee..64f3739a0c33 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>> interrupt-names = "eventq", "gerror", "priq";
>> dma-coherent;
>> #iommu-cells = <1>;
>> - status = "disabled";
>> + status = "okay";
>
> Which file disabled it?
>
> Best regards,
> Krzysztof
Hi Dinh, Krzysztof
Thank you for the review and feedback!
Addressing Dinh's comment — the commit header has been updated to follow
the subsystem naming convention.
Addressing Krzysztof's question — the SMMU was disabled in
socfpga_agilex5.dtsi itself, where the node is defined with status =
"disabled". This has been clarified in the updated commit message.
https://lore.kernel.org/all/20260604105020.24782-1-muhammad.nazim.amirul.nazle.asmade@altera.com/
https://lore.kernel.org/all/20260604105020.24782-2-muhammad.nazim.amirul.nazle.asmade@altera.com/
https://lore.kernel.org/all/20260604105020.24782-3-muhammad.nazim.amirul.nazle.asmade@altera.com/
BR,
Nazim
next prev parent reply other threads:[~2026-06-04 10:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 8:00 [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC muhammad.nazim.amirul.nazle.asmade
2026-05-15 8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade
2026-05-15 11:51 ` Dinh Nguyen
2026-05-30 11:11 ` Krzysztof Kozlowski
2026-06-04 10:55 ` Nazle Asmade, Muhammad Nazim Amirul [this message]
2026-06-04 11:15 ` Krzysztof Kozlowski
2026-06-04 12:00 ` Nazle Asmade, Muhammad Nazim Amirul
2026-06-04 12:42 ` Krzysztof Kozlowski
2026-06-05 2:31 ` Nazle Asmade, Muhammad Nazim Amirul
2026-05-15 8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade
2026-05-15 11:52 ` Dinh Nguyen
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