Re: [PATCH 0/5] drm/rockchip: vop2: Fix layer cfg done timeout on multi-output setups

[Cristian Ciocaltea <cristian.ciocaltea@collabora.com>]

Hi Andy,

On 6/1/26 1:54 PM, Andy Yan wrote:
> Hello Cristian,
> 
> On 5/5/26 02:23, Cristian Ciocaltea wrote:
>> On RK3588/RK3568 boards with multiple active display outputs, start/stop
>> transitions may trigger a timeout during overlay layer configuration:
>>
>>    rockchip-drm display-subsystem: [drm] *ERROR* wait layer cfg done timeout
>>
>> The shared OVL_LAYER_SEL and OVL_PORT_SEL shadow registers are committed
>> to the active configuration at the vsync of whichever Video Port is
>> selected by LAYERSEL_REGDONE_SEL.  When two Video Ports race through
>> atomic commits, rk3568_vop2_setup_layer_mixer() has two issues that
>> cause the wait to poll for a value the hardware might not be able to
>> produce.
>>
>> Patch 1 fixes passing the wrong target to the wait function, since the
>> expected value was already overwritten with the current VP's new
>> layer_sel before reaching the wait.
>>
>> Patch 2 moves the wait before the LAYERSEL_REGDONE_SEL switch, so the
>> previous VP's vsync can still latch the pending configuration.
>>
>> Patches 3 through 5 contain only minor follow-up cleanup.
>>
>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> 
> 
> Thank you very much for your work, these fixes all look sensible.

Thanks for checking this out!

> However, I haven't been able to construct a scenario via weston that
> reproduce these issues. Could you please tell me how you triggered them?

It was really tricky to reproduce - a customer usecase repeatedly restarting one
of their apps under a customized Weston, and all that when having both HDMI
output ports active, where at least one drives a 4K display.

Regards,
Cristian