From: Adrian Hunter <adrian.hunter@intel.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
riteshh@codeaurora.org
Cc: thierry.reding@gmail.com, jonathanh@nvidia.com, anrao@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V1 09/11] mmc: cqhci: add CQHCI_SSC1 register CBC field mask
Date: Fri, 8 Mar 2019 14:14:36 +0200 [thread overview]
Message-ID: <47d5ee65-4614-59e3-4b23-b67030b2f5d2@intel.com> (raw)
In-Reply-To: <1551504025-3541-9-git-send-email-skomatineni@nvidia.com>
On 2/03/19 7:20 AM, Sowjanya Komatineni wrote:
> This patch adds define for CBC field mask of the register
> CQHCI_SSC1.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/cqhci.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index f96d8565cc07..f1dc48c7436f 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -88,6 +88,7 @@
>
> /* send status config 1 */
> #define CQHCI_SSC1 0x40
> +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
>
> /* send status config 2 */
> #define CQHCI_SSC2 0x44
>
next prev parent reply other threads:[~2019-03-08 12:16 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-02 5:20 [PATCH V1 01/11] mmc: tegra: fix ddr signaling for non-ddr modes Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 02/11] mmc: sdhci: allow host to specify maximum tuning loops Sowjanya Komatineni
2019-03-08 11:50 ` Adrian Hunter
2019-03-02 5:20 ` [PATCH V1 03/11] mmc: sdhci: add support for post tuning process Sowjanya Komatineni
2019-03-08 11:55 ` Adrian Hunter
2019-03-02 5:20 ` [PATCH V1 04/11] mmc: tegra: update hw " Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 05/11] dt-bindings: mmc: tegra: document Tegra194 compatible string Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 06/11] arm64: tegra: fix default tap and trim values Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 07/11] mmc: cqhci: add quirk for setting DCMD CMD_TIMING Sowjanya Komatineni
2019-03-06 13:00 ` Adrian Hunter
2019-03-07 2:43 ` Ritesh Harjani
2019-03-07 18:16 ` Sowjanya Komatineni
2019-03-08 12:29 ` Adrian Hunter
2019-03-09 5:14 ` Sowjanya Komatineni
2019-03-13 2:31 ` Ritesh Harjani
2019-03-13 9:56 ` Hunter, Adrian
2019-03-13 15:47 ` Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 08/11] mmc: tegra: add Tegra186 WAR for CQE Sowjanya Komatineni
2019-03-02 5:20 ` [PATCH V1 09/11] mmc: cqhci: add CQHCI_SSC1 register CBC field mask Sowjanya Komatineni
2019-03-08 12:14 ` Adrian Hunter [this message]
2019-03-02 5:20 ` [PATCH V1 10/11] mmc: tegra: fix CQE resume sequence Sowjanya Komatineni
2019-03-08 12:59 ` Adrian Hunter
2019-03-02 5:20 ` [PATCH V1 11/11] arm64: tegra: enable command queue for tegra186 sdmmc4 Sowjanya Komatineni
2019-03-07 21:31 ` [PATCH V1 01/11] mmc: tegra: fix ddr signaling for non-ddr modes Jon Hunter
2019-03-08 11:44 ` Adrian Hunter
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