Re: [PATCH] x86/Kconfig: Make X86_UMIP to cover Zhaoxin CPUs too

[Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>]

On 05/03/2020 23:59, Sean Christopherson wrote:
> On Thu, Mar 05, 2020 at 11:40:02AM +0800, Tony W Wang-oc wrote:
>>
>> On 05/03/2020 01:13, Sean Christopherson wrote:
>>> On Wed, Mar 04, 2020 at 10:18:05AM +0800, Tony W Wang-oc wrote:
>>>> New Zhaoxin family 7 CPUs support the UMIP (User-Mode Instruction
>>>> Prevention) feature. So, modify X86_UMIP depends on Zhaoxin CPUs too.
>>>>
>>>> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
>>>> ---
>>>>  arch/x86/Kconfig | 2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
>>>> index 16a4b39..ca4beb8 100644
>>>> --- a/arch/x86/Kconfig
>>>> +++ b/arch/x86/Kconfig
>>>> @@ -1877,7 +1877,7 @@ config X86_SMAP
>>>>  
>>>>  config X86_UMIP
>>>>  	def_bool y
>>>> -	depends on CPU_SUP_INTEL || CPU_SUP_AMD
>>>> +	depends on CPU_SUP_INTEL || CPU_SUP_AMD || CPU_SUP_CENTAUR || CPU_SUP_ZHAOXIN
>>>
>>> The changelog only mentions Zhaoxin, but this also adds Centaur...
>>
>> Sorry for this. Some Centaur family 7 CPUs also support the UMIP
>> feature, so will resend this patch as a patch series.
> 
> Oooh, can you point me at architectural documentation for Centaur family 7?
> I've been trying to track down Centaur documentation for CPUID behavior.
> .
> 

Centaur uses CPUID.(EAX=7,ECX=0):ECX[bit 2] indicates UMIP feature, that
is compatible with Intel's UMIP implementation.

Sincerely
TonyWWang-oc