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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479111561c2sm28158805e9.4.2025.11.27.02.16.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Nov 2025 02:16:07 -0800 (PST) Message-ID: <47e40d25-59c8-4dc8-aa55-4a1da6adf85f@linaro.org> Date: Thu, 27 Nov 2025 10:16:05 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 5/5] media: qcom: camss: vfe: Add support for VFE 1080 To: Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251120-add-support-for-camss-on-kaanapali-v7-0-de27f9a67ce6@oss.qualcomm.com> <20251120-add-support-for-camss-on-kaanapali-v7-5-de27f9a67ce6@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20251120-add-support-for-camss-on-kaanapali-v7-5-de27f9a67ce6@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 21/11/2025 04:43, Hangxiang Ma wrote: > Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC. > > The FULL front end modules in Kaanapali camera subsystem are called TFEs > (Thin Front End), however, retaining the name VFE at places to maintain > consistency and avoid unnecessary code changes. > > This change limits the VFE output lines to 3 for now as constrained by > the CAMSS driver framework. > > Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be > issued after all of the CSID configuration has been done. Additionally, > the number of AUP_UPDATEs should match the number of buffers enqueued to > the write master while it's being enabled. > > Although the real time data from TFE goes through the RT_CAMNOC, we are > required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for > the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, > to ensure that both of the latter are idle after reset. > > Co-developed-by: Atiya Kailany > Signed-off-by: Atiya Kailany > Signed-off-by: Hangxiang Ma > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > drivers/media/platform/qcom/camss/camss-vfe-1080.c | 197 +++++++++++++++++++++ > drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- > drivers/media/platform/qcom/camss/camss-vfe.h | 2 + > drivers/media/platform/qcom/camss/camss.c | 143 +++++++++++++++ > 5 files changed, 350 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index 3a7ed4f5a004..dc41b0d6dc21 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -22,6 +22,7 @@ qcom-camss-objs += \ > camss-vfe-340.o \ > camss-vfe-480.o \ > camss-vfe-680.o \ > + camss-vfe-1080.o \ > camss-vfe-gen3.o \ > camss-vfe-gen1.o \ > camss-vfe.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c > new file mode 100644 > index 000000000000..9ad3dee2e80b > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c > @@ -0,0 +1,197 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * camss-vfe-1080.c > + * > + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080 > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > +#include > +#include > +#include > + > +#include "camss.h" > +#include "camss-vfe.h" > + > +/* VFE-1080 Bus Register Base Addresses */ > +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) > + > +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) > +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > + > +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128) > + > +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100) > +#define WM_CFG_EN BIT(0) > +#define WM_VIR_FRM_EN BIT(1) > +#define WM_CFG_MODE BIT(16) > +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100) > +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100) > +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100) > +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) > +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100) > +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) > +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100) > + > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100) > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100) > + > +/* VFE lite has no such registers */ > +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100) > + > +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100) > +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100) > + > +/* > + * IFE write master client IDs > + * > + * VIDEO_FULL 0 > + * VIDEO_DC4_Y 1 > + * VIDEO_DC4_C 2 > + * VIDEO_DC16_Y 3 > + * VIDEO_DC16_C 4 > + * DISPLAY_DS2_Y 5 > + * DISPLAY_DS2_C 6 > + * FD_Y 7 > + * FD_C 8 > + * PIXEL_RAW 9 > + * STATS_AEC_BG 10 > + * STATS_AEC_BHIST 11 > + * STATS_TINTLESS_BG 12 > + * STATS_AWB_BG 13 > + * STATS_AWB_BFW 14 > + * STATS_AF_BHIST 15 > + * STATS_ALSC_BG 16 > + * STATS_FLICKER_BAYERRS 17 > + * STATS_TMC_BHIST 18 > + * PDAF_0 19 > + * PDAF_1 20 > + * PDAF_2 21 > + * PDAF_3 22 > + * RDI0 23 > + * RDI1 24 > + * RDI2 25 > + * RDI3 26 > + * RDI4 27 > + * > + * IFE Lite write master client IDs > + * > + * RDI0 0 > + * RDI1 1 > + * RDI2 2 > + * RDI3 3 > + * GAMMA 4 > + * STATES_BE 5 > + */ > +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) > + > +static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line) > +{ > + struct v4l2_pix_format_mplane *pix = > + &line->video_out.active_fmt.fmt.pix_mp; > + > + wm = RDI_WM(wm); > + > + /* no clock gating at bus input */ > + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > + > + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); > + > + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, > + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); > + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), > + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); > + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); > + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > + > + /* no dropped frames, one irq per frame */ > + if (!vfe_is_lite(vfe)) { > + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); > + } > + > + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); > + > + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); > + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); > + > + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm) > +{ > + wm = RDI_WM(wm); > + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr, > + struct vfe_line *line) > +{ > + wm = RDI_WM(wm); > + writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); > + > + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); > +} > + > +static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, false); > +} > + > +static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe, > + enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, true); > +} > + > +static const struct camss_video_ops vfe_video_ops_1080 = { > + .queue_buffer = vfe_queue_buffer_v2, > + .flush_buffers = vfe_flush_buffers, > +}; > + > +static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe) > +{ > + vfe->video_ops = vfe_video_ops_1080; > +} > + > +static void vfe_global_reset_1080(struct vfe_device *vfe) > +{ > + vfe_isr_reset_ack(vfe); > +} > + > +static irqreturn_t vfe_isr_1080(int irq, void *dev) > +{ > + /* nop */ > + return IRQ_HANDLED; > +} > + > +static int vfe_halt_1080(struct vfe_device *vfe) > +{ > + /* rely on vfe_disable_output() to stop the VFE */ > + return 0; > +} > + > +const struct vfe_hw_ops vfe_ops_1080 = { > + .global_reset = vfe_global_reset_1080, > + .hw_version = vfe_hw_version, > + .isr = vfe_isr_1080, > + .pm_domain_off = vfe_pm_domain_off, > + .pm_domain_on = vfe_pm_domain_on, > + .reg_update = vfe_reg_update_1080, > + .reg_update_clear = vfe_reg_update_clear_1080, > + .subdev_init = vfe_subdev_init_1080, > + .vfe_disable = vfe_disable, > + .vfe_enable = vfe_enable_v2, > + .vfe_halt = vfe_halt_1080, > + .vfe_wm_start = vfe_wm_start_1080, > + .vfe_wm_stop = vfe_wm_stop_1080, > + .vfe_buf_done = vfe_buf_done, > + .vfe_wm_update = vfe_wm_update_1080, > +}; Since this patch isn't applied, you should repost this file with the right name. --- bod