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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id d3sm6658015edv.87.2021.09.15.01.24.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Sep 2021 01:24:35 -0700 (PDT) Subject: Re: [PATCH 2/6] clk: samsung: clk-pll: Implement pll0822x PLL type To: Sam Protsenko , Sylwester Nawrocki , =?UTF-8?Q?Pawe=c5=82_Chmiel?= , Chanwoo Choi , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette Cc: Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org References: <20210914155607.14122-1-semen.protsenko@linaro.org> <20210914155607.14122-3-semen.protsenko@linaro.org> From: Krzysztof Kozlowski Message-ID: <47e5b93a-27b4-2188-7b1e-fd2c1b2379d3@canonical.com> Date: Wed, 15 Sep 2021 10:24:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210914155607.14122-3-semen.protsenko@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/09/2021 17:56, Sam Protsenko wrote: > pll0822x PLL is used in Exynos850 SoC for top-level integer PLLs. The > code was derived from very similar pll35xx type, with next differences: > > 1. Lock time for pll0822x is 150*P_DIV, when for pll35xx it's 270*P_DIV > 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require > performing PLL lock procedure (which is done in pll35xx > implementation) > > When defining pll0822x type, CON3 register offset should be provided as > a "con" parameter of PLL() macro, like this: > > PLL(pll_0822x, 0, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > exynos850_shared0_pll_rates), > > To define PLL rates table, one can use PLL_35XX_RATE() macro, e.g.: > > PLL_35XX_RATE(26 * MHZ, 1600 * MHZ, 800, 13, 0) > > as it's completely appropriate for pl0822x type and there is no sense in > duplicating that. > > If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be > possible to set new rate, with next error showing in kernel log: > > Could not lock PLL fout_shared1_pll > > That can happen for example if bootloader clears that bit beforehand. > PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was > cleared, it's assumed it was done for a reason and it shouldn't be > possible to change that PLL's rate at all. > > Signed-off-by: Sam Protsenko > --- > drivers/clk/samsung/clk-pll.c | 91 +++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 92 insertions(+) > Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof