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Wed, 17 Sep 2025 12:48:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFNUj9iiTkIiBdyuwHV1qhUP3oLhWgJBvCsq76MF3fHoniGNQ6FCUfXLye/WwI6WYVKAKakdA== X-Received: by 2002:a17:90b:1f84:b0:32e:64ca:e84e with SMTP id 98e67ed59e1d1-32ee3ef7071mr4546578a91.15.1758138489768; Wed, 17 Sep 2025 12:48:09 -0700 (PDT) Received: from [10.216.40.15] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cfec3f454sm199284b3a.75.2025.09.17.12.47.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Sep 2025 12:48:09 -0700 (PDT) Message-ID: <47f7a917-3bb6-4331-8813-49f6646333e5@oss.qualcomm.com> Date: Thu, 18 Sep 2025 01:17:58 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 5/5] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring To: Jonathan Cameron Cc: robh@kernel.org, krzysztof.kozlowski@linaro.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org References: <20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com> <20250826083657.4005727-6-jishnu.prakash@oss.qualcomm.com> <20250830185809.5bc010cb@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20250830185809.5bc010cb@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: wP04h9CBPp_i6XIUOk7PuVAsmqIoHBaW X-Authority-Analysis: v=2.4 cv=bIMWIO+Z c=1 sm=1 tr=0 ts=68cb107b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=-qQjPGFekNv0xv3-IhUA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX3FIPBL5yQxE+ y5CyW0kC2Jb3lzx1OYa+W09bQEUuVeMcq4poDERByDJcy/YXIBM59Q5eZAvma9Z0LujT89bYzyr aef9munB+Rz8Xch3ZZg+/CefFu6/HkKHNSnZDkV96LH7QDw0MmSaaHV5aRf+pPS0aD6KLOMdAVI C8rhAghken7IBSGv0qfXPoqZT7ThvtjnXMFPdDmkssfT1Jl6dm9gvAbDX6AeINMWWXfSWVpPKAi IQZOdPQagqcgQZNR2IVWPcoeEIsh4iBDbd7jTuZTA87bL/nZfZVQasX5SFqb18OQLdcjSXzy+gQ AnA8UAOFYpTTwtI+jCd3A2fOggPlX0TpLatAAj0QYH48N4quJ4FMNOm6Xix500Snw+wcxNoSPJq m7cIS7+J X-Proofpoint-ORIG-GUID: wP04h9CBPp_i6XIUOk7PuVAsmqIoHBaW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Hi Jonathan, On 8/30/2025 11:28 PM, Jonathan Cameron wrote: > On Tue, 26 Aug 2025 14:06:57 +0530 > Jishnu Prakash wrote: > >> Add support for ADC_TM part of PMIC5 Gen3. >> >> This is an auxiliary driver under the Gen3 ADC driver, which implements the >> threshold setting and interrupt generating functionalities of QCOM ADC_TM >> drivers, used to support thermal trip points. >> >> Signed-off-by: Jishnu Prakash > Hi Jishnu, > > A few comment inline from a fresh read > > Jonathan > > ... >> + >> + adc_tm5->dev = dev; >> + adc_tm5->dev_data = aux_dev_wrapper->dev_data; >> + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels; >> + adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels, >> + sizeof(*adc_tm5->chan_props), GFP_KERNEL); >> + if (!adc_tm5->chan_props) >> + return -ENOMEM; >> + >> + for (i = 0; i < adc_tm5->nchannels; i++) { >> + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i]; >> + adc_tm5->chan_props[i].timer = MEAS_INT_1S; >> + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8; >> + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8; >> + adc_tm5->chan_props[i].chip = adc_tm5; >> + } >> + >> + ret = devm_add_action_or_reset(dev, adc5_gen3_disable, adc_tm5); > > I'd normally expect a pairing of a devm action with whatever it is undoing. > If not add a comment for why that isn't the case here. This is meant to disable all ADC_TM channels in case of a probe failure. But thinking more on it, ADC_TM channels could be enabled only by the thermal framework calling the .set_trip function and that could happen only after this line at the end of the probe, for thermal framework registration: return adc_tm5_register_tzd(adc_tm5); So I think it makes more sense to move this call to near the end of the probe and to make it devm_add_action() instead of devm_add_action_or_reset(). I'll also add a comment mentioning what it does. I'll also address all your other comments in the next patch series. Thanks, Jishnu > >> + if (ret) >> + return ret; >> + >> + INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work); > >> +} >> + >> +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = { >> + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, >> + {} > > For IIO drivers I'm trying to slowly standardize some formatting choices. > For these I picked (for no particular reason) > { } > >> +};