From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2130AC433EF for ; Thu, 12 May 2022 11:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352923AbiELLF2 (ORCPT ); Thu, 12 May 2022 07:05:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229789AbiELLFZ (ORCPT ); Thu, 12 May 2022 07:05:25 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE5A222EA40; Thu, 12 May 2022 04:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652353525; x=1683889525; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=3uK8K761LCbMLiiXm5n4vA0kexSUsrfEfvE68CU0Ygw=; b=TCluLWCRLDoFcszrAIvPejtDG6jn24GX1T34ZSzfbMlt0dJcGOyIH634 e/H7eyUrsyKCLPclv6u+xbHlCuUtH+WckLkbq9/lyP2ym+r2rHIbMp68C /0xEp4Ary+4CsTDj+Bzml00fKnSFYrja8vM3cq/FhYQ2yM56iPGAFgZBj s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 12 May 2022 04:05:25 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2022 04:05:24 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 12 May 2022 04:05:23 -0700 Received: from [10.50.8.133] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 12 May 2022 04:05:17 -0700 Message-ID: <48087fad-a48a-e5f4-5840-a74be5057537@quicinc.com> Date: Thu, 12 May 2022 16:35:14 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH V3] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs Content-Language: en-US To: Shreyas K K , Will Deacon , Catalin Marinas , Marc Zyngier , Suzuki K Poulose , Mark Rutland CC: Andre Przywara , , , , Jeffrey Hugo , Rajendra Nayak , Prasanna Kumar References: <20220512110134.12179-1-quic_shrekk@quicinc.com> From: Sai Prakash Ranjan In-Reply-To: <20220512110134.12179-1-quic_shrekk@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/12/2022 4:31 PM, Shreyas K K wrote: > Add KRYO4XX gold/big cores to the list of CPUs that need the > repeat TLBI workaround. Apply this to the affected > KRYO4XX cores (rcpe to rfpe). > > The variant and revision bits are implementation defined and are > different from the their Cortex CPU counterparts on which they are > based on, i.e., (r0p0 to r3p0) is equivalent to (rcpe to rfpe). > > Signed-off-by: Shreyas K K > --- > > Changes in v2: > * r2p0 and r3p0 are also affected by this erratum. > * Add the corresponding cores (repe and rfpe) making the range rcpe to rfpe. > > Changes in v3: > * Fix the CPU model macro. > > Documentation/arm64/silicon-errata.rst | 3 +++ > arch/arm64/kernel/cpu_errata.c | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 466cb9e89047..d27db84d585e 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -189,6 +189,9 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 | > +----------------+-----------------+-----------------+-----------------------------+ > +| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 | > ++----------------+-----------------+-----------------+-----------------------------+ > + > +----------------+-----------------+-----------------+-----------------------------+ > | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 4c9b5b4b7a0b..a0f3d0aaa3c5 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { > #ifdef CONFIG_ARM64_ERRATUM_1286807 > { > ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), > + /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ > + ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), > }, > #endif > {}, Reviewed-by: Sai Prakash Ranjan Thanks, Sai