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Wed, 06 May 2026 21:09:10 -0700 (PDT) X-Received: by 2002:a17:90b:134d:b0:33b:b078:d6d3 with SMTP id 98e67ed59e1d1-365ac7757cemr6881514a91.23.1778126950094; Wed, 06 May 2026 21:09:10 -0700 (PDT) Received: from [10.218.34.110] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2babadef249sm8030845ad.59.2026.05.06.21.09.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 May 2026 21:09:09 -0700 (PDT) Message-ID: <4809a7f7-8ec1-4f72-9154-8ca01111f4a5@oss.qualcomm.com> Date: Thu, 7 May 2026 09:39:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pinctrl: qcom: Unconditionally mark gpio as wakeup enable To: Linus Walleij Cc: Bjorn Andersson , Neil Armstrong , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260430-enable_wakeup_capable_gpios-v1-1-5de39bf06094@oss.qualcomm.com> Content-Language: en-US From: Sneh Mankad In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDAzNyBTYWx0ZWRfX0wuL5jivYGCx nA08qibFvzU/R1dpkjEEFjljosaInwswhif5tr44MKSUXucyffubBrW/p5zaFNHa/SqAU/baNQX 4u/rJmzqIDQexQwppCCBAtFQDs6WGJWtRlKYz0Qxa98MkRixJGHIg2HuHbtcUFH1GfLnB0pCp2H /XolC5GcsuXB6c9a3zvd4yHOZjdtfp0SjVj9eEMbvbEGyV9Jut+FOzogtYi7r32q9soJhEfr7Md SAZ4/u8OFHCanQzVUw7kSLY10foFpxzzIVznYWuJOiKxZAquzNpTe2c+5hNyghUwD3YZZT6dcIU QkEub35e1J921mVuxF92x6MZVHR7uG2ListHTJ+uoqiGe4GW9R4W1hZ/Oumr7Z+Pl9GYBpZZYeP qD1x6EXdR6y7ZUsgiQG+tzkU4rdjfSywDuaWGt/HZWx+3nVf0RoOosma3hYFTrLg+JgZwMstnWn nF3/v/XcHBAcnBENGhQ== X-Proofpoint-GUID: Za42AtpRaiePxWgp0UErBIZGoz5RXYqs X-Proofpoint-ORIG-GUID: Za42AtpRaiePxWgp0UErBIZGoz5RXYqs X-Authority-Analysis: v=2.4 cv=K4IS2SWI c=1 sm=1 tr=0 ts=69fc1067 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=_3-bX4vkxkCJ1edF7K4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070037 On 05-May-26 3:58 PM, Linus Walleij wrote: > On Thu, Apr 30, 2026 at 7:54 AM Sneh Mankad > wrote: > >> The wakeup enable bit needs to be set irrespective of the SoC using PDC or >> MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded >> to parent irqchip. >> >> This is set only for PDC irqchip using additional check skip_wake_irqs >> making it impossible for MPM irqchip to detect the GPIO interrupt during >> SoC low power mode since for MPM irqchip the skip_wake_irqs is always >> false. >> >> Remove skip_wake_irqs condition when setting wakeup enable bit to allow >> forwarding GPIO interrupts for SoCs using MPM irqchip too. >> >> Fixes: 76b446f5b86e ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") >> Signed-off-by: Sneh Mankad > Good work here, also super-dangerous so if some more Qualcomm > engineers could pitch in on this patch it'd be great. > > Is this an urgent (-rc) or nonurgent (next) fix? > > Yours, > Linus Walleij Its fine if it gets picked in the next release. Thanks Sneh