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[83.9.1.117]) by smtp.gmail.com with ESMTPSA id 2-20020a170906210200b00888f92f0708sm8229934ejt.15.2023.02.14.03.25.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Feb 2023 03:25:03 -0800 (PST) Message-ID: <48364c3f-699d-ce14-37c4-53bf4a90bc23@linaro.org> Date: Tue, 14 Feb 2023 12:25:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [Freedreno] [PATCH 09/14] drm/msm/a6xx: Fix some A619 tunables Content-Language: en-US To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org, freedreno@lists.freedesktop.org, Akhil P Oommen , David Airlie , Abhinav Kumar , dri-devel@lists.freedesktop.org, Douglas Anderson , Rob Clark , Daniel Vetter , Dmitry Baryshkov , marijn.suijten@somainline.org, Sean Paul , Chia-I Wu , linux-kernel@vger.kernel.org References: <20230126151618.225127-1-konrad.dybcio@linaro.org> <20230126151618.225127-10-konrad.dybcio@linaro.org> <20230208182101.53ykatzah6zvpy76@amazon.com> From: Konrad Dybcio In-Reply-To: <20230208182101.53ykatzah6zvpy76@amazon.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8.02.2023 19:21, Jordan Crouse wrote: > On Thu, Jan 26, 2023 at 04:16:13PM +0100, Konrad Dybcio wrote: >> Adreno 619 expects some tunables to be set differently. Make up for it. >> >> Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") >> Signed-off-by: Konrad Dybcio >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 7a480705f407..f34ab3f39f09 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1171,6 +1171,8 @@ static int hw_init(struct msm_gpu *gpu) >> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); >> else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) >> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); >> + else if (adreno_is_a619(adreno_gpu)) >> + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); >> else if (adreno_is_a610(adreno_gpu)) >> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); >> else >> @@ -1188,7 +1190,9 @@ static int hw_init(struct msm_gpu *gpu) >> a6xx_set_ubwc_config(gpu); >> >> /* Enable fault detection */ >> - if (adreno_is_a610(adreno_gpu)) >> + if (adreno_is_a619(adreno_gpu)) >> + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); >> + else if (adreno_is_a610(adreno_gpu)) >> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); >> else >> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); > > The number appended to the register is the number of clock ticks to wait > before declaring a hang. 0x3fffff happens to be the largest value that > can be set for the a6xx family (excepting the 610 which, IIRC, used older > hardware that had a smaller field for the counter). Makes sense! Downstream the > number would creep up over time as unexplained hangs were discovered and > diagnosed or covered up as "just wait longer". lol.. > > So in theory you could leave this with the "default value" or even bump > up the default value to 0x3fffff for all targets if you wanted to. An > alternate solution (that downstream does) is to put this as a > pre-defined configuration in gpulist[]. I'm not sure it's a good idea to let things loose, as that may let some bugs slip through.. Perhaps let's leave that as-is until we have a seriously otherwise-unresolvable situation.. Konrad > > Jordan