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Wed, 12 Aug 2026 22:29:10 +0000 Message-ID: <483c5b72-5f39-435c-b6f7-0f9f4f7abff3@intel.com> Date: Wed, 12 Aug 2026 15:29:07 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix To: Babu Moger , , , , CC: , , , , , , , , , , , , , References: <96992e30d6c02ebb7bdb58f2d8060bfd61274649.1784739398.git.babu.moger@amd.com> Content-Language: en-US From: Reinette Chatre In-Reply-To: <96992e30d6c02ebb7bdb58f2d8060bfd61274649.1784739398.git.babu.moger@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MW4PR04CA0069.namprd04.prod.outlook.com (2603:10b6:303:6b::14) To SJ2PR11MB8370.namprd11.prod.outlook.com (2603:10b6:a03:540::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR11MB8370:EE_|DS0PR11MB8231:EE_ X-MS-Office365-Filtering-Correlation-Id: 41e9b875-58c4-4fdc-7259-08def8c120d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|23010399003|1800799024|376014|7416014|6133799003|56012099006|10067099003|11063799006|18002099003|22082099003; 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(looks like all of them were defined this way) "were defined" -> "are defined"? > with an MSR_IA32_ prefix even though they are AMD-specific and unrelated > to Intel's IA32 resctrl MSRs. The MSR_IA32_ prefix is misleading when > reading or grepping the codebase alongside the Intel MSR_IA32_* resctrl > definitions in msr-index.h. > > Rename the AMD resctrl MSR definitions, update all call sites, and keep > the tools copy of msr-index.h in sync: > > MSR_IA32_MBA_BW_BASE -> MSR_AMD_MBA_BW_BASE > MSR_IA32_SMBA_BW_BASE -> MSR_AMD_SMBA_BW_BASE > MSR_IA32_L3_QOS_ABMC_CFG -> MSR_AMD_L3_QOS_ABMC_CFG > MSR_IA32_L3_QOS_EXT_CFG -> MSR_AMD_L3_QOS_EXT_CFG > MSR_IA32_EVT_CFG_BASE -> MSR_AMD_EVT_CFG_BASE > > No functional changes. > > Suggested-by: Borislav Petkov (AMD) > Signed-off-by: Babu Moger > --- ... > @@ -114,7 +114,7 @@ static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) > /* Walking r->ctrl_domains, ensure it can't race with cpuhp */ > lockdep_assert_cpus_held(); > > - /* Update MSR_IA32_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ > + /* Update MSR_AMD_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ I think this is a good opportunity to remove the redundant text when referring to these MSRs. For example, "Update MSR_AMD_L3_QOS_EXT_CFG MSR ..." can just be "Update MSR_AMD_L3_QOS_EXT_CFG ..." This is indeed done by this patch, but not consistently. > list_for_each_entry_rcu(d, &r->ctrl_domains, hdr.list, lockdep_is_cpus_held()) > on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1); > } ... > diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c > index 3838e0a13d36..a2c9acc7aec8 100644 > --- a/arch/x86/kernel/cpu/resctrl/monitor.c > +++ b/arch/x86/kernel/cpu/resctrl/monitor.c > @@ -498,9 +498,9 @@ static void resctrl_abmc_set_one_amd(void *arg) > bool *enable = arg; > > if (*enable) > - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); > + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); > else > - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); > + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); > } > > /* The comment appearing at this point contains "L3_QOS_EXT_CFG MSR" - the changelog mentions support for "grepping the codebase" making this a candidate for changing also? > @@ -542,7 +542,7 @@ static void resctrl_abmc_config_one_amd(void *info) > { > union l3_qos_abmc_cfg *abmc_cfg = info; > > - wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full); > + wrmsrq(MSR_AMD_L3_QOS_ABMC_CFG, abmc_cfg->full); > } > > /* ... > diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c > index 30df902ea776..30c4c57e0e4c 100644 > --- a/fs/resctrl/rdtgroup.c > +++ b/fs/resctrl/rdtgroup.c > @@ -1785,8 +1785,8 @@ static void mbm_config_write_domain(struct rdt_resource *r, > mon_info.mon_config = val; > > /* > - * Update MSR_IA32_EVT_CFG_BASE MSR on one of the CPUs in the > - * domain. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE > + * Update MSR_AMD_EVT_CFG_BASE MSR on one of the CPUs in the "MSR_AMD_EVT_CFG_BASE MSR" -> "MSR_AMD_EVT_CFG_BASE"? > + * domain. The MSRs offset from MSR_AMD_EVT_CFG_BASE Here the redundant text is indeed removed. > * are scoped at the domain level. Writing any of these MSRs > * on one CPU is observed by all the CPUs in the domain. > */ I just have these nits. The patch looks good to me. Reinette